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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-exynos4/setup-sdhci.c
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/* linux/arch/arm/mach-exynos4/setup-sdhci.c

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 *

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 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

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 *		http://www.samsung.com

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 *

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 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)

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 *

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 * This program is free software; you can redistribute it and/or modify

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 * it under the terms of the GNU General Public License version 2 as

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 * published by the Free Software Foundation.

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*/

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#include <linux/kernel.h>

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#include <linux/types.h>

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#include <linux/interrupt.h>

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#include <linux/platform_device.h>

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#include <linux/io.h>

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#include <linux/mmc/card.h>

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#include <linux/mmc/host.h>

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#include <plat/regs-sdhci.h>

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/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */

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char *exynos4_hsmmc_clksrcs[4] = {

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	[0] = NULL,

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	[1] = NULL,

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	[2] = "sclk_mmc",	/* mmc_bus */

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	[3] = NULL,

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};

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void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,

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				  struct mmc_ios *ios, struct mmc_card *card)

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{

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	u32 ctrl2, ctrl3;

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	/* don't need to alter anything according to card-type */

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	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);

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	/* select base clock source to HCLK */

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	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;

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	/*

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	 * clear async mode, enable conflict mask, rx feedback ctrl, SD

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	 * clk hold and no use debounce count

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	 */

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	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |

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		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |

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		  S3C_SDHCI_CTRL2_ENFBCLKRX |

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		  S3C_SDHCI_CTRL2_DFCNT_NONE |

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		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);

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	/* Tx and Rx feedback clock delay control */

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	if (ios->clock < 25 * 1000000)

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		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |

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			 S3C_SDHCI_CTRL3_FCSEL2 |

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			 S3C_SDHCI_CTRL3_FCSEL1 |

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			 S3C_SDHCI_CTRL3_FCSEL0);

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	else

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		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);

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	writel(ctrl2, r + S3C_SDHCI_CONTROL2);

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	writel(ctrl3, r + S3C_SDHCI_CONTROL3);

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}

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