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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
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/*

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 * arch/arm/mach-ixp23xx/include/mach/ixdp2351.h

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 *

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 * Register and other defines for IXDP2351

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 *

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 * Copyright (c) 2002-2004 Intel Corp.

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 * Copytight (c) 2005 MontaVista Software, Inc.

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 *

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 * This program is free software; you can redistribute it and/or modify it

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 * under the terms of the GNU General Public License as published by the

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 * Free Software Foundation; either version 2 of the License, or (at your

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 * option) any later version.

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 */

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#ifndef __ASM_ARCH_IXDP2351_H

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#define __ASM_ARCH_IXDP2351_H

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/*

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 * NP module memory map

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 */

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#define IXDP2351_NP_PHYS_BASE		(IXP23XX_EXP_BUS_CS4_BASE)

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#define IXDP2351_NP_PHYS_SIZE		0x00100000

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#define IXDP2351_NP_VIRT_BASE		0xeff00000

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#define IXDP2351_VIRT_CS8900_BASE	(IXDP2351_NP_VIRT_BASE)

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#define IXDP2351_VIRT_CS8900_END	(IXDP2351_VIRT_CS8900_BASE + 16)

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#define IXDP2351_VIRT_NP_CPLD_BASE 	(IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)

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#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))

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#define IXDP2351_NP_CPLD_RESET1_REG	IXDP2351_NP_CPLD_REG(0x00)

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#define IXDP2351_NP_CPLD_LED_REG	IXDP2351_NP_CPLD_REG(0x02)

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#define IXDP2351_NP_CPLD_VERSION_REG	IXDP2351_NP_CPLD_REG(0x04)

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/*

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 * Base board module memory map

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 */

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#define IXDP2351_BB_BASE_PHYS		(IXP23XX_EXP_BUS_CS5_BASE)

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#define IXDP2351_BB_SIZE		0x01000000

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#define IXDP2351_BB_BASE_VIRT		(0xee000000)

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#define IXDP2351_BB_AREA_BASE(offset)	(IXDP2351_BB_BASE_VIRT + offset)

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#define IXDP2351_VIRT_NVRAM_BASE	IXDP2351_BB_AREA_BASE(0x0)

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#define IXDP2351_NVRAM_SIZE		(0x20000)

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#define IXDP2351_VIRT_MB_IXF1104_BASE	IXDP2351_BB_AREA_BASE(0x00020000)

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#define IXDP2351_VIRT_ADD_UART_BASE	IXDP2351_BB_AREA_BASE(0x000240C0)

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#define IXDP2351_VIRT_FIC_BASE		IXDP2351_BB_AREA_BASE(0x00200000)

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#define IXDP2351_VIRT_DB0_BASE		IXDP2351_BB_AREA_BASE(0x00400000)

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#define IXDP2351_VIRT_DB1_BASE		IXDP2351_BB_AREA_BASE(0x00600000)

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#define IXDP2351_VIRT_CPLD_BASE		IXDP2351_BB_AREA_BASE(0x00024000)

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/*

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 * On board CPLD registers

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 */

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#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))

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#define IXDP2351_CPLD_RESET0_REG	IXDP2351_CPLD_BB_REG(0x00)

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#define IXDP2351_CPLD_RESET1_REG	IXDP2351_CPLD_BB_REG(0x04)

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#define IXDP2351_CPLD_RESET1_MAGIC 	0x55AA

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#define IXDP2351_CPLD_RESET1_ENABLE 	0x8000

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#define IXDP2351_CPLD_FPGA_CONFIG_REG	IXDP2351_CPLD_BB_REG(0x08)

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#define IXDP2351_CPLD_INTB_MASK_SET_REG	IXDP2351_CPLD_BB_REG(0x10)

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#define IXDP2351_CPLD_INTA_MASK_SET_REG	IXDP2351_CPLD_BB_REG(0x14)

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#define IXDP2351_CPLD_INTB_STAT_REG	IXDP2351_CPLD_BB_REG(0x18)

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#define IXDP2351_CPLD_INTA_STAT_REG	IXDP2351_CPLD_BB_REG(0x1C)

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#define IXDP2351_CPLD_INTB_RAW_REG	IXDP2351_CPLD_BB_REG(0x20)	/* read */

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#define IXDP2351_CPLD_INTA_RAW_REG	IXDP2351_CPLD_BB_REG(0x24)	/* read */

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#define IXDP2351_CPLD_INTB_MASK_CLR_REG	IXDP2351_CPLD_INTB_RAW_REG	/* write */

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#define IXDP2351_CPLD_INTA_MASK_CLR_REG	IXDP2351_CPLD_INTA_RAW_REG	/* write */

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#define IXDP2351_CPLD_INTB_SIM_REG	IXDP2351_CPLD_BB_REG(0x28)

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#define IXDP2351_CPLD_INTA_SIM_REG	IXDP2351_CPLD_BB_REG(0x2C)

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	/* Interrupt bits are defined in irqs.h */

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#define IXDP2351_CPLD_BB_GBE0_REG	IXDP2351_CPLD_BB_REG(0x30)

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#define IXDP2351_CPLD_BB_GBE1_REG	IXDP2351_CPLD_BB_REG(0x34)

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/* #define IXDP2351_CPLD_BB_MISC_REG	IXDP2351_CPLD_REG(0x1C) */

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/* #define IXDP2351_CPLD_BB_MISC_REV_MASK	0xFF		*/

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/* #define IXDP2351_CPLD_BB_GDXCS0_REG	IXDP2351_CPLD_REG(0x24) */

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/* #define IXDP2351_CPLD_BB_GDXCS1_REG	IXDP2351_CPLD_REG(0x28) */

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/* #define IXDP2351_CPLD_BB_CLOCK_REG	IXDP2351_CPLD_REG(0x04) */

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#endif

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