Path: blob/master/arch/arm/mach-ks8695/include/mach/regs-irq.h
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/*1* arch/arm/mach-ks8695/include/mach/regs-irq.h2*3* Copyright (C) 2006 Ben Dooks <[email protected]>4* Copyright (C) 2006 Simtec Electronics5*6* KS8695 - IRQ registers and bit definitions7*8* This file is licensed under the terms of the GNU General Public9* License version 2. This program is licensed "as is" without any10* warranty of any kind, whether express or implied.11*/1213#ifndef KS8695_IRQ_H14#define KS8695_IRQ_H1516#define KS8695_IRQ_OFFSET (0xF0000 + 0xE200)17#define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET)18#define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET)192021/*22* Interrupt Controller registers23*/24#define KS8695_INTMC (0x00) /* Mode Control Register */25#define KS8695_INTEN (0x04) /* Interrupt Enable Register */26#define KS8695_INTST (0x08) /* Interrupt Status Register */27#define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */28#define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */29#define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */30#define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */31#define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */32#define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */33#define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */34#define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */35#define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */36#define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */37#define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */383940#endif414243