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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-loki/addr-map.c
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/*

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 * arch/arm/mach-loki/addr-map.c

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 *

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 * Address map functions for Marvell Loki (88RC8480) SoCs

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 *

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 * This file is licensed under the terms of the GNU General Public

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 * License version 2.  This program is licensed "as is" without any

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 * warranty of any kind, whether express or implied.

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 */

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#include <linux/kernel.h>

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#include <linux/init.h>

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#include <linux/mbus.h>

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#include <linux/io.h>

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#include <mach/hardware.h>

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#include "common.h"

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/*

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 * Generic Address Decode Windows bit settings

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 */

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#define TARGET_DDR		0

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#define TARGET_DEV_BUS		1

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#define TARGET_PCIE0		3

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#define TARGET_PCIE1		4

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#define ATTR_DEV_BOOT		0x0f

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#define ATTR_DEV_CS2		0x1b

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#define ATTR_DEV_CS1		0x1d

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#define ATTR_DEV_CS0		0x1e

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#define ATTR_PCIE_IO		0x51

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#define ATTR_PCIE_MEM		0x59

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/*

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 * Helpers to get DDR bank info

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 */

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#define DDR_SIZE_CS(n)		DDR_REG(0x1500 + ((n) << 3))

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#define DDR_BASE_CS(n)		DDR_REG(0x1504 + ((n) << 3))

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/*

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 * CPU Address Decode Windows registers

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 */

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#define BRIDGE_REG(x)		(BRIDGE_VIRT_BASE | (x))

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#define CPU_WIN_CTRL(n)		BRIDGE_REG(0x000 | ((n) << 4))

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#define CPU_WIN_BASE(n)		BRIDGE_REG(0x004 | ((n) << 4))

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#define CPU_WIN_REMAP_LO(n)	BRIDGE_REG(0x008 | ((n) << 4))

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#define CPU_WIN_REMAP_HI(n)	BRIDGE_REG(0x00c | ((n) << 4))

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struct mbus_dram_target_info loki_mbus_dram_info;

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static void __init setup_cpu_win(int win, u32 base, u32 size,

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				 u8 target, u8 attr, int remap)

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{

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	u32 ctrl;

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	base &= 0xffff0000;

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	ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;

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	writel(base, CPU_WIN_BASE(win));

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	writel(ctrl, CPU_WIN_CTRL(win));

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	if (win < 2) {

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		if (remap < 0)

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			remap = base;

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		writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));

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		writel(0, CPU_WIN_REMAP_HI(win));

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	}

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}

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void __init loki_setup_cpu_mbus(void)

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{

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	int i;

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	int cs;

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	/*

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	 * First, disable and clear windows.

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	 */

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	for (i = 0; i < 8; i++) {

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		writel(0, CPU_WIN_BASE(i));

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		writel(0, CPU_WIN_CTRL(i));

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		if (i < 2) {

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			writel(0, CPU_WIN_REMAP_LO(i));

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			writel(0, CPU_WIN_REMAP_HI(i));

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		}

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	}

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	/*

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	 * Setup windows for PCIe IO+MEM space.

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	 */

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	setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,

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		      TARGET_PCIE0, ATTR_PCIE_MEM, -1);

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	setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,

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		      TARGET_PCIE1, ATTR_PCIE_MEM, -1);

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	/*

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	 * Setup MBUS dram target info.

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	 */

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	loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;

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	for (i = 0, cs = 0; i < 4; i++) {

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		u32 base = readl(DDR_BASE_CS(i));

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		u32 size = readl(DDR_SIZE_CS(i));

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		/*

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		 * Chip select enabled?

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		 */

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		if (size & 1) {

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			struct mbus_dram_window *w;

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			w = &loki_mbus_dram_info.cs[cs++];

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			w->cs_index = i;

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			w->mbus_attr = 0xf & ~(1 << i);

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			w->base = base & 0xffff0000;

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			w->size = (size | 0x0000ffff) + 1;

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		}

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	}

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	loki_mbus_dram_info.num_cs = cs;

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}

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void __init loki_setup_dev_boot_win(u32 base, u32 size)

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{

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	setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);

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}

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