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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-mmp/include/mach/regs-apbc.h
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/*

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 * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h

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 *

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 *   Application Peripheral Bus Clock Unit

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 *

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 * This program is free software; you can redistribute it and/or modify

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 * it under the terms of the GNU General Public License version 2 as

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 * published by the Free Software Foundation.

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 */

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#ifndef __ASM_MACH_REGS_APBC_H

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#define __ASM_MACH_REGS_APBC_H

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#include <mach/addr-map.h>

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#define APBC_VIRT_BASE	(APB_VIRT_BASE + 0x015000)

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#define APBC_REG(x)	(APBC_VIRT_BASE + (x))

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/*

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 * APB clock register offsets for PXA168

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 */

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#define APBC_PXA168_UART1	APBC_REG(0x000)

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#define APBC_PXA168_UART2	APBC_REG(0x004)

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#define APBC_PXA168_GPIO	APBC_REG(0x008)

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#define APBC_PXA168_PWM1	APBC_REG(0x00c)

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#define APBC_PXA168_PWM2	APBC_REG(0x010)

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#define APBC_PXA168_PWM3	APBC_REG(0x014)

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#define APBC_PXA168_PWM4	APBC_REG(0x018)

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#define APBC_PXA168_RTC		APBC_REG(0x028)

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#define APBC_PXA168_TWSI0	APBC_REG(0x02c)

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#define APBC_PXA168_KPC		APBC_REG(0x030)

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#define APBC_PXA168_TIMERS	APBC_REG(0x034)

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#define APBC_PXA168_AIB		APBC_REG(0x03c)

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#define APBC_PXA168_SW_JTAG	APBC_REG(0x040)

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#define APBC_PXA168_ONEWIRE	APBC_REG(0x048)

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#define APBC_PXA168_ASFAR	APBC_REG(0x050)

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#define APBC_PXA168_ASSAR	APBC_REG(0x054)

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#define APBC_PXA168_TWSI1	APBC_REG(0x06c)

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#define APBC_PXA168_UART3	APBC_REG(0x070)

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#define APBC_PXA168_AC97	APBC_REG(0x084)

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#define APBC_PXA168_SSP1	APBC_REG(0x81c)

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#define APBC_PXA168_SSP2	APBC_REG(0x820)

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#define APBC_PXA168_SSP3	APBC_REG(0x84c)

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#define APBC_PXA168_SSP4	APBC_REG(0x858)

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#define APBC_PXA168_SSP5	APBC_REG(0x85c)

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/*

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 * APB Clock register offsets for PXA910

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 */

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#define APBC_PXA910_UART0	APBC_REG(0x000)

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#define APBC_PXA910_UART1	APBC_REG(0x004)

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#define APBC_PXA910_GPIO	APBC_REG(0x008)

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#define APBC_PXA910_PWM1	APBC_REG(0x00c)

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#define APBC_PXA910_PWM2	APBC_REG(0x010)

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#define APBC_PXA910_PWM3	APBC_REG(0x014)

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#define APBC_PXA910_PWM4	APBC_REG(0x018)

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#define APBC_PXA910_SSP1	APBC_REG(0x01c)

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#define APBC_PXA910_SSP2	APBC_REG(0x020)

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#define APBC_PXA910_IPC		APBC_REG(0x024)

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#define APBC_PXA910_TWSI0	APBC_REG(0x02c)

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#define APBC_PXA910_KPC		APBC_REG(0x030)

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#define APBC_PXA910_TIMERS	APBC_REG(0x034)

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#define APBC_PXA910_TBROT	APBC_REG(0x038)

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#define APBC_PXA910_AIB		APBC_REG(0x03c)

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#define APBC_PXA910_SW_JTAG	APBC_REG(0x040)

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#define APBC_PXA910_TIMERS1	APBC_REG(0x044)

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#define APBC_PXA910_ONEWIRE	APBC_REG(0x048)

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#define APBC_PXA910_SSP3	APBC_REG(0x04c)

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#define APBC_PXA910_ASFAR	APBC_REG(0x050)

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#define APBC_PXA910_ASSAR	APBC_REG(0x054)

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/*

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 * APB Clock register offsets for MMP2

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 */

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#define APBC_MMP2_RTC		APBC_REG(0x000)

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#define APBC_MMP2_TWSI1		APBC_REG(0x004)

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#define APBC_MMP2_TWSI2		APBC_REG(0x008)

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#define APBC_MMP2_TWSI3		APBC_REG(0x00c)

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#define APBC_MMP2_TWSI4		APBC_REG(0x010)

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#define APBC_MMP2_ONEWIRE	APBC_REG(0x014)

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#define APBC_MMP2_KPC		APBC_REG(0x018)

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#define APBC_MMP2_TB_ROTARY	APBC_REG(0x01c)

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#define APBC_MMP2_SW_JTAG	APBC_REG(0x020)

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#define APBC_MMP2_TIMERS	APBC_REG(0x024)

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#define APBC_MMP2_UART1		APBC_REG(0x02c)

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#define APBC_MMP2_UART2		APBC_REG(0x030)

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#define APBC_MMP2_UART3		APBC_REG(0x034)

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#define APBC_MMP2_GPIO		APBC_REG(0x038)

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#define APBC_MMP2_PWM0		APBC_REG(0x03c)

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#define APBC_MMP2_PWM1		APBC_REG(0x040)

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#define APBC_MMP2_PWM2		APBC_REG(0x044)

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#define APBC_MMP2_PWM3		APBC_REG(0x048)

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#define APBC_MMP2_SSP0		APBC_REG(0x04c)

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#define APBC_MMP2_SSP1		APBC_REG(0x050)

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#define APBC_MMP2_SSP2		APBC_REG(0x054)

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#define APBC_MMP2_SSP3		APBC_REG(0x058)

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#define APBC_MMP2_SSP4		APBC_REG(0x05c)

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#define APBC_MMP2_SSP5		APBC_REG(0x060)

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#define APBC_MMP2_AIB		APBC_REG(0x064)

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#define APBC_MMP2_ASFAR		APBC_REG(0x068)

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#define APBC_MMP2_ASSAR		APBC_REG(0x06c)

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#define APBC_MMP2_USIM		APBC_REG(0x070)

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#define APBC_MMP2_MPMU		APBC_REG(0x074)

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#define APBC_MMP2_IPC		APBC_REG(0x078)

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#define APBC_MMP2_TWSI5		APBC_REG(0x07c)

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#define APBC_MMP2_TWSI6		APBC_REG(0x080)

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#define APBC_MMP2_TWSI_INTSTS	APBC_REG(0x084)

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#define APBC_MMP2_UART4		APBC_REG(0x088)

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#define APBC_MMP2_RIPC		APBC_REG(0x08c)

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#define APBC_MMP2_THSENS1	APBC_REG(0x090)	/* Thermal Sensor */

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#define APBC_MMP2_THSENS_INTSTS	APBC_REG(0x0a4)

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/* Common APB clock register bit definitions */

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#define APBC_APBCLK	(1 << 0)  /* APB Bus Clock Enable */

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#define APBC_FNCLK	(1 << 1)  /* Functional Clock Enable */

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#define APBC_RST	(1 << 2)  /* Reset Generation */

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/* Functional Clock Selection Mask */

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#define APBC_FNCLKSEL(x)	(((x) & 0xf) << 4)

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#endif /* __ASM_MACH_REGS_APBC_H */

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