Path: blob/master/arch/arm/mach-mmp/include/mach/regs-apmu.h
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/*1* linux/arch/arm/mach-mmp/include/mach/regs-apmu.h2*3* Application Subsystem Power Management Unit4*5* This program is free software; you can redistribute it and/or modify6* it under the terms of the GNU General Public License version 2 as7* published by the Free Software Foundation.8*/910#ifndef __ASM_MACH_REGS_APMU_H11#define __ASM_MACH_REGS_APMU_H1213#include <mach/addr-map.h>1415#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800)16#define APMU_REG(x) (APMU_VIRT_BASE + (x))1718/* Clock Reset Control */19#define APMU_IRE APMU_REG(0x048)20#define APMU_LCD APMU_REG(0x04c)21#define APMU_CCIC APMU_REG(0x050)22#define APMU_SDH0 APMU_REG(0x054)23#define APMU_SDH1 APMU_REG(0x058)24#define APMU_USB APMU_REG(0x05c)25#define APMU_NAND APMU_REG(0x060)26#define APMU_DMA APMU_REG(0x064)27#define APMU_GEU APMU_REG(0x068)28#define APMU_BUS APMU_REG(0x06c)29#define APMU_SDH2 APMU_REG(0x0e8)30#define APMU_SDH3 APMU_REG(0x0ec)3132#define APMU_FNCLK_EN (1 << 4)33#define APMU_AXICLK_EN (1 << 3)34#define APMU_FNRST_DIS (1 << 1)35#define APMU_AXIRST_DIS (1 << 0)3637/* Wake Clear Register */38#define APMU_WAKE_CLR APMU_REG(0x07c)3940#define APMU_PXA168_KP_WAKE_CLR (1 << 7)41#define APMU_PXA168_CFI_WAKE_CLR (1 << 6)42#define APMU_PXA168_XD_WAKE_CLR (1 << 5)43#define APMU_PXA168_MSP_WAKE_CLR (1 << 4)44#define APMU_PXA168_SD4_WAKE_CLR (1 << 3)45#define APMU_PXA168_SD3_WAKE_CLR (1 << 2)46#define APMU_PXA168_SD2_WAKE_CLR (1 << 1)47#define APMU_PXA168_SD1_WAKE_CLR (1 << 0)4849#endif /* __ASM_MACH_REGS_APMU_H */505152