Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
17686 views
1
/*

2
 * Low-level IRQ helper macros

3
 *

4
 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.

5
 *

6
 * This file is licensed under  the terms of the GNU General Public

7
 * License version 2. This program is licensed "as is" without any

8
 * warranty of any kind, whether express or implied.

9
 */

10


11
#include <mach/hardware.h>

12
#include <asm/hardware/gic.h>

13


14
	.macro	disable_fiq

15
	.endm

16


17
	.macro  get_irqnr_preamble, base, tmp

18
	ldr	\base, =gic_cpu_base_addr

19
	ldr	\base, [\base]

20
	.endm

21


22
	.macro  arch_ret_to_user, tmp1, tmp2

23
	.endm

24


25
	/*

26
	 * The interrupt numbering scheme is defined in the

27
	 * interrupt controller spec.  To wit:

28
	 *

29
	 * Migrated the code from ARM MP port to be more consistent

30
	 * with interrupt processing , the following still holds true

31
	 * however, all interrupts are treated the same regardless of

32
	 * if they are local IPI or PPI

33
	 *

34
	 * Interrupts 0-15 are IPI

35
	 * 16-31 are PPI

36
	 *   (16-18 are the timers)

37
	 * 32-1020 are global

38
	 * 1021-1022 are reserved

39
	 * 1023 is "spurious" (no interrupt)

40
	 *

41
	 * A simple read from the controller will tell us the number of the

42
	 * highest priority enabled interrupt.  We then just need to check

43
	 * whether it is in the valid range for an IRQ (0-1020 inclusive).

44
	 *

45
	 * Base ARM code assumes that the local (private) peripheral interrupts

46
	 * are not valid, we treat them differently, in that the privates are

47
	 * handled like normal shared interrupts with the exception that only

48
	 * one processor can register the interrupt and the handler must be

49
	 * the same for all processors.

50
	 */

51


52
	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp

53


54
	ldr  \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,

55
						   9-0 =int # */

56


57
	bic     \irqnr, \irqstat, #0x1c00	@mask src

58
	cmp     \irqnr, #15

59
	ldr		\tmp, =1021

60
	cmpcc	\irqnr, \irqnr

61
	cmpne	\irqnr, \tmp

62
	cmpcs	\irqnr, \irqnr

63


64
	.endm

65


66
	/* We assume that irqstat (the raw value of the IRQ acknowledge

67
	 * register) is preserved from the macro above.

68
	 * If there is an IPI, we immediately signal end of interrupt on the

69
	 * controller, since this requires the original irqstat value which

70
	 * we won't easily be able to recreate later.

71
	 */

72
	.macro test_for_ipi, irqnr, irqstat, base, tmp

73
    bic \irqnr, \irqstat, #0x1c00

74
    cmp \irqnr, #16

75
    strcc   \irqstat, [\base, #GIC_CPU_EOI]

76
    cmpcs   \irqnr, \irqnr

77
	.endm

78


79
	/* As above, this assumes that irqstat and base are preserved.. */

80


81
	.macro test_for_ltirq, irqnr, irqstat, base, tmp

82
    bic \irqnr, \irqstat, #0x1c00

83
    mov     \tmp, #0

84
    cmp \irqnr, #16

85
    moveq   \tmp, #1

86
    streq   \irqstat, [\base, #GIC_CPU_EOI]

87
    cmp \tmp, #0

88
	.endm

89


90