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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-msm/include/mach/irqs-7x30.h
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/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.

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 *

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 * This program is free software; you can redistribute it and/or modify

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 * it under the terms of the GNU General Public License version 2 and

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 * only version 2 as published by the Free Software Foundation.

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 *

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 * This program is distributed in the hope that it will be useful,

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 * but WITHOUT ANY WARRANTY; without even the implied warranty of

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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

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 * GNU General Public License for more details.

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 */

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#ifndef __ASM_ARCH_MSM_IRQS_7X30_H

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#define __ASM_ARCH_MSM_IRQS_7X30_H

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/* MSM ACPU Interrupt Numbers */

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#define INT_DEBUG_TIMER_EXP	0

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#define INT_GPT0_TIMER_EXP	1

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#define INT_GPT1_TIMER_EXP	2

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#define INT_WDT0_ACCSCSSBARK	3

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#define INT_WDT1_ACCSCSSBARK	4

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#define INT_AVS_SVIC		5

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#define INT_AVS_SVIC_SW_DONE	6

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#define INT_SC_DBG_RX_FULL	7

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#define INT_SC_DBG_TX_EMPTY	8

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#define INT_ARM11_PM		9

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#define INT_AVS_REQ_DOWN	10

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#define INT_AVS_REQ_UP		11

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#define INT_SC_ACG		12

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/* SCSS_VICFIQSTS0[13:15] are RESERVED */

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#define INT_L2_SVICCPUIRPTREQ	16

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#define INT_L2_SVICDMANSIRPTREQ 17

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#define INT_L2_SVICDMASIRPTREQ  18

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#define INT_L2_SVICSLVIRPTREQ	19

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#define INT_AD5A_MPROC_APPS_0	20

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#define INT_AD5A_MPROC_APPS_1	21

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#define INT_A9_M2A_0		22

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#define INT_A9_M2A_1		23

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#define INT_A9_M2A_2		24

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#define INT_A9_M2A_3		25

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#define INT_A9_M2A_4		26

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#define INT_A9_M2A_5		27

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#define INT_A9_M2A_6		28

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#define INT_A9_M2A_7		29

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#define INT_A9_M2A_8		30

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#define INT_A9_M2A_9		31

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#define INT_AXI_EBI1_SC		(32 + 0)

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#define INT_IMEM_ERR		(32 + 1)

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#define INT_AXI_EBI0_SC		(32 + 2)

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#define INT_PBUS_SC_IRQC	(32 + 3)

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#define INT_PERPH_BUS_BPM	(32 + 4)

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#define INT_CC_TEMP_SENSE	(32 + 5)

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#define INT_UXMC_EBI0		(32 + 6)

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#define INT_UXMC_EBI1		(32 + 7)

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#define INT_EBI2_OP_DONE	(32 + 8)

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#define INT_EBI2_WR_ER_DONE	(32 + 9)

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#define INT_TCSR_SPSS_CE	(32 + 10)

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#define INT_EMDH		(32 + 11)

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#define INT_PMDH		(32 + 12)

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#define INT_MDC			(32 + 13)

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#define INT_MIDI_TO_SUPSS	(32 + 14)

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#define INT_LPA_2		(32 + 15)

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#define INT_GPIO_GROUP1_SECURE	(32 + 16)

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#define INT_GPIO_GROUP2_SECURE	(32 + 17)

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#define INT_GPIO_GROUP1		(32 + 18)

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#define INT_GPIO_GROUP2		(32 + 19)

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#define INT_MPRPH_SOFTRESET	(32 + 20)

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#define INT_PWB_I2C		(32 + 21)

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#define INT_PWB_I2C_2		(32 + 22)

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#define INT_TSSC_SAMPLE		(32 + 23)

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#define INT_TSSC_PENUP		(32 + 24)

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#define INT_TCHSCRN_SSBI	(32 + 25)

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#define INT_FM_RDS		(32 + 26)

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#define INT_KEYSENSE 		(32 + 27)

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#define INT_USB_OTG_HS		(32 + 28)

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#define INT_USB_OTG_HS2		(32 + 29)

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#define INT_USB_OTG_HS3		(32 + 30)

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#define INT_CSI			(32 + 31)

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#define INT_SPI_OUTPUT		(64 + 0)

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#define INT_SPI_INPUT		(64 + 1)

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#define INT_SPI_ERROR		(64 + 2)

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#define INT_UART1		(64 + 3)

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#define INT_UART1_RX		(64 + 4)

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#define INT_UART2		(64 + 5)

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#define INT_UART2_RX		(64 + 6)

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#define INT_UART3		(64 + 7)

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#define INT_UART3_RX		(64 + 8)

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#define INT_UART1DM_IRQ		(64 + 9)

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#define INT_UART1DM_RX		(64 + 10)

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#define INT_UART2DM_IRQ		(64 + 11)

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#define INT_UART2DM_RX		(64 + 12)

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#define INT_TSIF		(64 + 13)

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#define INT_ADM_SC1		(64 + 14)

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#define INT_ADM_SC2		(64 + 15)

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#define INT_MDP			(64 + 16)

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#define INT_VPE			(64 + 17)

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#define INT_GRP_2D		(64 + 18)

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#define INT_GRP_3D		(64 + 19)

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#define INT_ROTATOR		(64 + 20)

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#define INT_MFC720		(64 + 21)

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#define INT_JPEG		(64 + 22)

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#define INT_VFE			(64 + 23)

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#define INT_TV_ENC		(64 + 24)

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#define INT_PMIC_SSBI		(64 + 25)

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#define INT_MPM_1		(64 + 26)

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#define INT_TCSR_SPSS_SAMPLE	(64 + 27)

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#define INT_TCSR_SPSS_PENUP	(64 + 28)

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#define INT_MPM_2		(64 + 29)

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#define INT_SDC1_0		(64 + 30)

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#define INT_SDC1_1		(64 + 31)

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#define INT_SDC3_0		(96 + 0)

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#define INT_SDC3_1		(96 + 1)

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#define INT_SDC2_0		(96 + 2)

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#define INT_SDC2_1		(96 + 3)

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#define INT_SDC4_0		(96 + 4)

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#define INT_SDC4_1		(96 + 5)

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#define INT_PWB_QUP_IN		(96 + 6)

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#define INT_PWB_QUP_OUT		(96 + 7)

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#define INT_PWB_QUP_ERR		(96 + 8)

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#define INT_SCSS_WDT0_BITE	(96 + 9)

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/* SCSS_VICFIQSTS3[10:31] are RESERVED */

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/* Retrofit universal macro names */

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#define INT_ADM_AARM		INT_ADM_SC2

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#define INT_USB_HS   		INT_USB_OTG_HS

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#define INT_USB_OTG   		INT_USB_OTG_HS

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#define INT_TCHSCRN1 		INT_TSSC_SAMPLE

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#define INT_TCHSCRN2 		INT_TSSC_PENUP

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#define INT_GP_TIMER_EXP 	INT_GPT0_TIMER_EXP

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#define INT_ADSP_A11 		INT_AD5A_MPROC_APPS_0

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#define INT_ADSP_A9_A11 	INT_AD5A_MPROC_APPS_1

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#define INT_MDDI_EXT		INT_EMDH

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#define INT_MDDI_PRI		INT_PMDH

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#define INT_MDDI_CLIENT		INT_MDC

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#define INT_NAND_WR_ER_DONE	INT_EBI2_WR_ER_DONE

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#define INT_NAND_OP_DONE	INT_EBI2_OP_DONE

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#define NR_MSM_IRQS		128

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#define NR_GPIO_IRQS		182

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#define PMIC8058_IRQ_BASE	(NR_MSM_IRQS + NR_GPIO_IRQS)

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#define NR_PMIC8058_GPIO_IRQS	40

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#define NR_PMIC8058_MPP_IRQS	12

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#define NR_PMIC8058_MISC_IRQS	8

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#define NR_PMIC8058_IRQS	(NR_PMIC8058_GPIO_IRQS +\

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				NR_PMIC8058_MPP_IRQS +\

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				NR_PMIC8058_MISC_IRQS)

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#define NR_BOARD_IRQS		NR_PMIC8058_IRQS

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#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */

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