Path: blob/master/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
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/*1* Copyright (C) 2007 Google, Inc.2* Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.3* Author: Brian Swetland <[email protected]>4*5* This software is licensed under the terms of the GNU General Public6* License version 2, as published by the Free Software Foundation, and7* may be copied, distributed, and modified under those terms.8*9* This program is distributed in the hope that it will be useful,10* but WITHOUT ANY WARRANTY; without even the implied warranty of11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the12* GNU General Public License for more details.13*14*15* The MSM peripherals are spread all over across 768MB of physical16* space, which makes just having a simple IO_ADDRESS macro to slide17* them into the right virtual location rough. Instead, we will18* provide a master phys->virt mapping for peripherals here.19*20*/2122#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H23#define __ASM_ARCH_MSM_IOMAP_8X50_H2425/* Physical base address and size of peripherals.26* Ordered by the virtual base addresses they will be mapped at.27*28* MSM_VIC_BASE must be an value that can be loaded via a "mov"29* instruction, otherwise entry-macro.S will not compile.30*31* If you add or remove entries here, you'll want to edit the32* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your33* changes.34*35*/3637#define MSM_VIC_BASE IOMEM(0xE0000000)38#define MSM_VIC_PHYS 0xAC00000039#define MSM_VIC_SIZE SZ_4K4041#define QSD8X50_CSR_PHYS 0xAC10000042#define QSD8X50_CSR_SIZE SZ_4K4344#define MSM_DMOV_BASE IOMEM(0xE0002000)45#define MSM_DMOV_PHYS 0xA970000046#define MSM_DMOV_SIZE SZ_4K4748#define MSM_GPIO1_BASE IOMEM(0xE0003000)49#define MSM_GPIO1_PHYS 0xA900000050#define MSM_GPIO1_SIZE SZ_4K5152#define MSM_GPIO2_BASE IOMEM(0xE0004000)53#define MSM_GPIO2_PHYS 0xA910000054#define MSM_GPIO2_SIZE SZ_4K5556#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)57#define MSM_CLK_CTL_PHYS 0xA860000058#define MSM_CLK_CTL_SIZE SZ_4K5960#define MSM_SIRC_BASE IOMEM(0xE1006000)61#define MSM_SIRC_PHYS 0xAC20000062#define MSM_SIRC_SIZE SZ_4K6364#define MSM_SCPLL_BASE IOMEM(0xE1007000)65#define MSM_SCPLL_PHYS 0xA880000066#define MSM_SCPLL_SIZE SZ_4K6768#ifdef CONFIG_MSM_SOC_REV_A69#define MSM_SMI_BASE 0xE000000070#else71#define MSM_SMI_BASE 0x0000000072#endif7374#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)75#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)76#define MSM_SHARED_RAM_SIZE SZ_1M7778#define MSM_UART1_PHYS 0xA9A0000079#define MSM_UART1_SIZE SZ_4K8081#define MSM_UART2_PHYS 0xA9B0000082#define MSM_UART2_SIZE SZ_4K8384#define MSM_UART3_PHYS 0xA9C0000085#define MSM_UART3_SIZE SZ_4K8687#ifdef CONFIG_MSM_DEBUG_UART88#define MSM_DEBUG_UART_BASE 0xE100000089#if CONFIG_MSM_DEBUG_UART == 190#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS91#elif CONFIG_MSM_DEBUG_UART == 292#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS93#elif CONFIG_MSM_DEBUG_UART == 394#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS95#endif96#define MSM_DEBUG_UART_SIZE SZ_4K97#endif9899#define MSM_MDC_BASE IOMEM(0xE0200000)100#define MSM_MDC_PHYS 0xAA500000101#define MSM_MDC_SIZE SZ_1M102103#define MSM_AD5_BASE IOMEM(0xE0300000)104#define MSM_AD5_PHYS 0xAC000000105#define MSM_AD5_SIZE (SZ_1M*13)106107108#define MSM_I2C_SIZE SZ_4K109#define MSM_I2C_PHYS 0xA9900000110111#define MSM_HSUSB_PHYS 0xA0800000112#define MSM_HSUSB_SIZE SZ_1K113114#define MSM_NAND_PHYS 0xA0A00000115116117#define MSM_TSIF_PHYS (0xa0100000)118#define MSM_TSIF_SIZE (0x200)119120#define MSM_TSSC_PHYS 0xAA300000121122#define MSM_UART1DM_PHYS 0xA0200000123#define MSM_UART2DM_PHYS 0xA0900000124125126#define MSM_SDC1_PHYS 0xA0300000127#define MSM_SDC1_SIZE SZ_4K128129#define MSM_SDC2_PHYS 0xA0400000130#define MSM_SDC2_SIZE SZ_4K131132#define MSM_SDC3_PHYS 0xA0500000133#define MSM_SDC3_SIZE SZ_4K134135#define MSM_SDC4_PHYS 0xA0600000136#define MSM_SDC4_SIZE SZ_4K137138#endif139140141