CoCalc -- crm

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/arm/mach-mx5/crm_regs.h
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/*
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 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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 *
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 * The code contained herein is licensed under the GNU General Public
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 * License. You may obtain a copy of the GNU General Public License
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 * Version 2 or later at the following locations:
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 *
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 * http://www.opensource.org/licenses/gpl-license.html
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 * http://www.gnu.org/copyleft/gpl.html
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 */
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#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
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#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
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#define MX51_CCM_BASE		MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
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#define MX51_DPLL1_BASE		MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
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#define MX51_DPLL2_BASE		MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
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#define MX51_DPLL3_BASE		MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
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#define MX51_CORTEXA8_BASE	MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
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#define MX51_GPC_BASE		MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
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/*MX53*/
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#define MX53_CCM_BASE		MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
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#define MX53_DPLL1_BASE		MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
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#define MX53_DPLL2_BASE		MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
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#define MX53_DPLL3_BASE		MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
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#define MX53_DPLL4_BASE		MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
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/* PLL Register Offsets */
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#define MXC_PLL_DP_CTL			0x00
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#define MXC_PLL_DP_CONFIG		0x04
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#define MXC_PLL_DP_OP			0x08
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#define MXC_PLL_DP_MFD			0x0C
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#define MXC_PLL_DP_MFN			0x10
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#define MXC_PLL_DP_MFNMINUS		0x14
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#define MXC_PLL_DP_MFNPLUS		0x18
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#define MXC_PLL_DP_HFS_OP		0x1C
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#define MXC_PLL_DP_HFS_MFD		0x20
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#define MXC_PLL_DP_HFS_MFN		0x24
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#define MXC_PLL_DP_MFN_TOGC		0x28
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#define MXC_PLL_DP_DESTAT		0x2c
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/* PLL Register Bit definitions */
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#define MXC_PLL_DP_CTL_MUL_CTRL		0x2000
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#define MXC_PLL_DP_CTL_DPDCK0_2_EN	0x1000
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#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET	12
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#define MXC_PLL_DP_CTL_ADE		0x800
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#define MXC_PLL_DP_CTL_REF_CLK_DIV	0x400
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#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK	(3 << 8)
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#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET	8
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#define MXC_PLL_DP_CTL_HFSM		0x80
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#define MXC_PLL_DP_CTL_PRE		0x40
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#define MXC_PLL_DP_CTL_UPEN		0x20
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#define MXC_PLL_DP_CTL_RST		0x10
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#define MXC_PLL_DP_CTL_RCP		0x8
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#define MXC_PLL_DP_CTL_PLM		0x4
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#define MXC_PLL_DP_CTL_BRM0		0x2
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#define MXC_PLL_DP_CTL_LRF		0x1
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#define MXC_PLL_DP_CONFIG_BIST		0x8
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#define MXC_PLL_DP_CONFIG_SJC_CE	0x4
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#define MXC_PLL_DP_CONFIG_AREN		0x2
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#define MXC_PLL_DP_CONFIG_LDREQ		0x1
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#define MXC_PLL_DP_OP_MFI_OFFSET	4
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#define MXC_PLL_DP_OP_MFI_MASK		(0xF << 4)
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#define MXC_PLL_DP_OP_PDF_OFFSET	0
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#define MXC_PLL_DP_OP_PDF_MASK		0xF
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#define MXC_PLL_DP_MFD_OFFSET		0
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#define MXC_PLL_DP_MFD_MASK		0x07FFFFFF
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#define MXC_PLL_DP_MFN_OFFSET		0x0
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#define MXC_PLL_DP_MFN_MASK		0x07FFFFFF
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#define MXC_PLL_DP_MFN_TOGC_TOG_DIS	(1 << 17)
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#define MXC_PLL_DP_MFN_TOGC_TOG_EN	(1 << 16)
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#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET	0x0
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#define MXC_PLL_DP_MFN_TOGC_CNT_MASK	0xFFFF
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#define MXC_PLL_DP_DESTAT_TOG_SEL	(1 << 31)
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#define MXC_PLL_DP_DESTAT_MFN		0x07FFFFFF
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/* Register addresses of CCM*/
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#define MXC_CCM_CCR		(MX51_CCM_BASE + 0x00)
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#define MXC_CCM_CCDR		(MX51_CCM_BASE + 0x04)
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#define MXC_CCM_CSR		(MX51_CCM_BASE + 0x08)
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#define MXC_CCM_CCSR		(MX51_CCM_BASE + 0x0C)
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#define MXC_CCM_CACRR		(MX51_CCM_BASE + 0x10)
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#define MXC_CCM_CBCDR		(MX51_CCM_BASE + 0x14)
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#define MXC_CCM_CBCMR		(MX51_CCM_BASE + 0x18)
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#define MXC_CCM_CSCMR1		(MX51_CCM_BASE + 0x1C)
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#define MXC_CCM_CSCMR2		(MX51_CCM_BASE + 0x20)
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#define MXC_CCM_CSCDR1		(MX51_CCM_BASE + 0x24)
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#define MXC_CCM_CS1CDR		(MX51_CCM_BASE + 0x28)
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#define MXC_CCM_CS2CDR		(MX51_CCM_BASE + 0x2C)
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#define MXC_CCM_CDCDR		(MX51_CCM_BASE + 0x30)
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#define MXC_CCM_CHSCDR		(MX51_CCM_BASE + 0x34)
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#define MXC_CCM_CSCDR2		(MX51_CCM_BASE + 0x38)
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#define MXC_CCM_CSCDR3		(MX51_CCM_BASE + 0x3C)
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#define MXC_CCM_CSCDR4		(MX51_CCM_BASE + 0x40)
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#define MXC_CCM_CWDR		(MX51_CCM_BASE + 0x44)
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#define MXC_CCM_CDHIPR		(MX51_CCM_BASE + 0x48)
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#define MXC_CCM_CDCR		(MX51_CCM_BASE + 0x4C)
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#define MXC_CCM_CTOR		(MX51_CCM_BASE + 0x50)
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#define MXC_CCM_CLPCR		(MX51_CCM_BASE + 0x54)
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#define MXC_CCM_CISR		(MX51_CCM_BASE + 0x58)
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#define MXC_CCM_CIMR		(MX51_CCM_BASE + 0x5C)
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#define MXC_CCM_CCOSR		(MX51_CCM_BASE + 0x60)
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#define MXC_CCM_CGPR		(MX51_CCM_BASE + 0x64)
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#define MXC_CCM_CCGR0		(MX51_CCM_BASE + 0x68)
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#define MXC_CCM_CCGR1		(MX51_CCM_BASE + 0x6C)
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#define MXC_CCM_CCGR2		(MX51_CCM_BASE + 0x70)
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#define MXC_CCM_CCGR3		(MX51_CCM_BASE + 0x74)
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#define MXC_CCM_CCGR4		(MX51_CCM_BASE + 0x78)
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#define MXC_CCM_CCGR5		(MX51_CCM_BASE + 0x7C)
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#define MXC_CCM_CCGR6		(MX51_CCM_BASE + 0x80)
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#define MXC_CCM_CMEOR		(MX51_CCM_BASE + 0x84)
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/* Define the bits in register CCR */
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#define MXC_CCM_CCR_COSC_EN		(1 << 12)
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#define MXC_CCM_CCR_FPM_MULT_MASK	(1 << 11)
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#define MXC_CCM_CCR_CAMP2_EN		(1 << 10)
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#define MXC_CCM_CCR_CAMP1_EN		(1 << 9)
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#define MXC_CCM_CCR_FPM_EN		(1 << 8)
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#define MXC_CCM_CCR_OSCNT_OFFSET	(0)
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#define MXC_CCM_CCR_OSCNT_MASK	(0xFF)
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/* Define the bits in register CCDR */
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#define MXC_CCM_CCDR_HSC_HS_MASK	(0x1 << 18)
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#define MXC_CCM_CCDR_IPU_HS_MASK	(0x1 << 17)
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#define MXC_CCM_CCDR_EMI_HS_MASK	(0x1 << 16)
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/* Define the bits in register CSR */
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#define MXC_CCM_CSR_COSR_READY	(1 << 5)
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#define MXC_CCM_CSR_LVS_VALUE	(1 << 4)
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#define MXC_CCM_CSR_CAMP2_READY	(1 << 3)
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#define MXC_CCM_CSR_CAMP1_READY	(1 << 2)
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#define MXC_CCM_CSR_FPM_READY	(1 << 1)
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#define MXC_CCM_CSR_REF_EN_B	(1 << 0)
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/* Define the bits in register CCSR */
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#define MXC_CCM_CCSR_LP_APM_SEL		(0x1 << 9)
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#define MXC_CCM_CCSR_STEP_SEL_OFFSET	(7)
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#define MXC_CCM_CCSR_STEP_SEL_MASK	(0x3 << 7)
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#define MXC_CCM_CCSR_STEP_SEL_LP_APM	   0
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#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
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#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
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#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
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#define MXC_CCM_CCSR_PLL2_PODF_OFFSET	(5)
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#define MXC_CCM_CCSR_PLL2_PODF_MASK	(0x3 << 5)
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#define MXC_CCM_CCSR_PLL3_PODF_OFFSET	(3)
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#define MXC_CCM_CCSR_PLL3_PODF_MASK	(0x3 << 3)
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#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL	(1 << 2) /* 0: pll1_main_clk,
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						    1: step_clk */
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#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL	(1 << 1)
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#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL	(1 << 0)
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/* Define the bits in register CACRR */
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#define MXC_CCM_CACRR_ARM_PODF_OFFSET	(0)
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#define MXC_CCM_CACRR_ARM_PODF_MASK	(0x7)
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/* Define the bits in register CBCDR */
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#define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
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#define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
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#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET		(30)
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#define MXC_CCM_CBCDR_DDR_HF_SEL		(0x1 << 30)
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#define MXC_CCM_CBCDR_DDR_PODF_OFFSET		(27)
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#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
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#define MXC_CCM_CBCDR_EMI_PODF_OFFSET		(22)
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#define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
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#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		(19)
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#define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
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#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		(16)
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#define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
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#define MXC_CCM_CBCDR_NFC_PODF_OFFSET		(13)
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#define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
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#define MXC_CCM_CBCDR_AHB_PODF_OFFSET		(10)
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#define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
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#define MXC_CCM_CBCDR_IPG_PODF_OFFSET		(8)
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#define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
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#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	(6)
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#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
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#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	(3)
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#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
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#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	(0)
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#define MXC_CCM_CBCDR_PERCLK_PODF_MASK		(0x7)
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/* Define the bits in register CBCMR */
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#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET	(14)
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#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK	(0x3 << 14)
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#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET	(12)
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#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK	(0x3 << 12)
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#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET	(10)
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#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK		(0x3 << 10)
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#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET	(8)
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#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK	(0x3 << 8)
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#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET	(6)
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#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK	(0x3 << 6)
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#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET	(4)
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#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK		(0x3 << 4)
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#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET	(14)
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#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK	(0x3 << 14)
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#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL	(0x1 << 1)
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#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL	(0x1 << 0)
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/* Define the bits in register CSCMR1 */
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#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		(30)
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#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
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#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		(28)
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#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
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#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		(26)
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#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
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#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		(24)
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#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
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#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		(22)
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#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
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#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	(20)
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#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
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#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL	(0x1 << 19)
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#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	(16)
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
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#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET	(16)
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#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK		(0x3 << 16)
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		(14)
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		(12)
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
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#define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
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#define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
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#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		(8)
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#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
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#define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
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#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
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#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		(4)
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#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
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#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		(2)
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#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
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#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
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#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		(0x1)
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/* Define the bits in register CSCMR2 */
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#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)		(26+n*3)
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#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)		(0x7 << (26+n*3))
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#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET		(24)
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#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK		(0x3 << 24)
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#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET		(22)
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#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK		(0x3 << 22)
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#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET		(20)
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#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK			(0x3 << 20)
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#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET		(18)
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#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK		(0x3 << 18)
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#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET		(16)
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#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK		(0x3 << 16)
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#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET		(14)
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#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK		(0x3 << 14)
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#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET		(12)
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#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK		(0x3 << 12)
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#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET		(10)
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#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK			(0x3 << 10)
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#define MXC_CCM_CSCMR2_SLIMBUS_COM			(0x1 << 9)
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#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET		(6)
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#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK		(0x7 << 6)
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#define MXC_CCM_CSCMR2_SPDIF1_COM			(1 << 5)
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#define MXC_CCM_CSCMR2_SPDIF0_COM			(1 << 4)
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#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET		(2)
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#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK		(0x3 << 2)
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#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET		(0)
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#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK		(0x3)
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/* Define the bits in register CSCDR1 */
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	(22)
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	(19)
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
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#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET	(22)
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#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK	(0x7 << 22)
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#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET	(19)
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#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK	(0x7 << 19)
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	(16)
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
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#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		(14)
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#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	(11)
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		(8)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		(6)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
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#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		(3)
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#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
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#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		(0)
294
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		(0x7)
295

296
/* Define the bits in register CS1CDR and CS2CDR */
297
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET		(22)
298
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK		(0x7 << 22)
299
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET		(16)
300
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK		(0x3F << 16)
301
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		(6)
302
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
303
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		(0)
304
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK		(0x3F)
305

306
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET		(22)
307
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK		(0x7 << 22)
308
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET		(16)
309
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK		(0x3F << 16)
310
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		(6)
311
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
312
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		(0)
313
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK		(0x3F)
314

315
/* Define the bits in register CDCDR */
316
#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET		(28)
317
#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK			(0x7 << 28)
318
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		(25)
319
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
320
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		(19)
321
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x3F << 19)
322
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		(16)
323
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 16)
324
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		(9)
325
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x3F << 9)
326
#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET		(6)
327
#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK			(0x7 << 6)
328
#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET		(3)
329
#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK			(0x7 << 3)
330
#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET		(0)
331
#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK			(0x7)
332

333
/* Define the bits in register CHSCCDR */
334
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET		(12)
335
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK		(0x7 << 12)
336
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET		(6)
337
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK		(0x3F << 6)
338
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET		(3)
339
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK		(0x7 << 3)
340
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET		(0)
341
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK		(0x7)
342

343
/* Define the bits in register CSCDR2 */
344
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		(25)
345
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
346
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		(19)
347
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
348
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		(16)
349
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
350
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		(9)
351
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
352
#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		(6)
353
#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
354
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		(0)
355
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		(0x3F)
356

357
/* Define the bits in register CSCDR3 */
358
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET		(16)
359
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK		(0x7 << 16)
360
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET		(9)
361
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK		(0x3F << 9)
362
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET		(6)
363
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK		(0x7 << 6)
364
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET		(0)
365
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK		(0x3F)
366

367
/* Define the bits in register CSCDR4 */
368
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET	(16)
369
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK		(0x7 << 16)
370
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET	(9)
371
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK		(0x3F << 9)
372
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET	(6)
373
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK		(0x7 << 6)
374
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET	(0)
375
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK		(0x3F)
376

377
/* Define the bits in register CDHIPR */
378
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
379
#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY		(1 << 8)
380
#define MXC_CCM_CDHIPR_DDR_PODF_BUSY			(1 << 7)
381
#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY			(1 << 6)
382
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
383
#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY	(1 << 4)
384
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 3)
385
#define MXC_CCM_CDHIPR_EMI_PODF_BUSY			(1 << 2)
386
#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY			(1 << 1)
387
#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY			(1 << 0)
388

389
/* Define the bits in register CDCR */
390
#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER		(0x1 << 2)
391
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET	(0)
392
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK		(0x3)
393

394
/* Define the bits in register CLPCR */
395
#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS		(0x1 << 23)
396
#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS		(0x1 << 22)
397
#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 21)
398
#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 25)
399
#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS	(0x1 << 20)
400
#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS		(0x1 << 19)
401
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS		(0x1 << 18)
402
#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS	(0x1 << 17)
403
#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS	(0x1 << 16)
404
#define MXC_CCM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
405
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET		(9)
406
#define MXC_CCM_CLPCR_STBY_COUNT_MASK		(0x3 << 9)
407
#define MXC_CCM_CLPCR_VSTBY			(0x1 << 8)
408
#define MXC_CCM_CLPCR_DIS_REF_OSC		(0x1 << 7)
409
#define MXC_CCM_CLPCR_SBYOS			(0x1 << 6)
410
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
411
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET	(3)
412
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK		(0x3 << 3)
413
#define MXC_CCM_CLPCR_LPM_OFFSET		(0)
414
#define MXC_CCM_CLPCR_LPM_MASK			(0x3)
415

416
/* Define the bits in register CISR */
417
#define MXC_CCM_CISR_ARM_PODF_LOADED			(0x1 << 25)
418
#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
419
#define MXC_CCM_CISR_AHB_PODF_LOADED			(0x1 << 20)
420
#define MXC_CCM_CISR_EMI_PODF_LOADED			(0x1 << 19)
421
#define MXC_CCM_CISR_AXI_B_PODF_LOADED			(0x1 << 18)
422
#define MXC_CCM_CISR_AXI_A_PODF_LOADED			(0x1 << 17)
423
#define MXC_CCM_CISR_DIVIDER_LOADED			(0x1 << 16)
424
#define MXC_CCM_CISR_COSC_READY				(0x1 << 6)
425
#define MXC_CCM_CISR_CKIH2_READY			(0x1 << 5)
426
#define MXC_CCM_CISR_CKIH_READY				(0x1 << 4)
427
#define MXC_CCM_CISR_FPM_READY				(0x1 << 3)
428
#define MXC_CCM_CISR_LRF_PLL3				(0x1 << 2)
429
#define MXC_CCM_CISR_LRF_PLL2				(0x1 << 1)
430
#define MXC_CCM_CISR_LRF_PLL1				(0x1)
431

432
/* Define the bits in register CIMR */
433
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(0x1 << 25)
434
#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
435
#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED		(0x1 << 20)
436
#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED		(0x1 << 19)
437
#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED		(0x1 << 18)
438
#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED		(0x1 << 17)
439
#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED		(0x1 << 16)
440
#define MXC_CCM_CIMR_MASK_COSC_READY			(0x1 << 5)
441
#define MXC_CCM_CIMR_MASK_CKIH_READY			(0x1 << 4)
442
#define MXC_CCM_CIMR_MASK_FPM_READY			(0x1 << 3)
443
#define MXC_CCM_CIMR_MASK_LRF_PLL3			(0x1 << 2)
444
#define MXC_CCM_CIMR_MASK_LRF_PLL2			(0x1 << 1)
445
#define MXC_CCM_CIMR_MASK_LRF_PLL1			(0x1)
446

447
/* Define the bits in register CCOSR */
448
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET			(0x1 << 24)
449
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET			(21)
450
#define MXC_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
451
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET			(16)
452
#define MXC_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
453
#define MXC_CCM_CCOSR_CKOL_EN				(0x1 << 7)
454
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET			(4)
455
#define MXC_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
456
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET			(0)
457
#define MXC_CCM_CCOSR_CKOL_SEL_MASK			(0xF)
458

459
/* Define the bits in registers CGPR */
460
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(0x1 << 4)
461
#define MXC_CCM_CGPR_FPM_SEL				(0x1 << 3)
462
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET		(0)
463
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK		(0x7)
464

465
/* Define the bits in registers CCGRx */
466
#define MXC_CCM_CCGRx_CG_MASK				0x3
467
#define MXC_CCM_CCGRx_MOD_OFF				0x0
468
#define MXC_CCM_CCGRx_MOD_ON				0x3
469
#define MXC_CCM_CCGRx_MOD_IDLE				0x1
470

471
#define MXC_CCM_CCGRx_CG15_MASK				(0x3 << 30)
472
#define MXC_CCM_CCGRx_CG14_MASK				(0x3 << 28)
473
#define MXC_CCM_CCGRx_CG13_MASK				(0x3 << 26)
474
#define MXC_CCM_CCGRx_CG12_MASK				(0x3 << 24)
475
#define MXC_CCM_CCGRx_CG11_MASK				(0x3 << 22)
476
#define MXC_CCM_CCGRx_CG10_MASK				(0x3 << 20)
477
#define MXC_CCM_CCGRx_CG9_MASK				(0x3 << 18)
478
#define MXC_CCM_CCGRx_CG8_MASK				(0x3 << 16)
479
#define MXC_CCM_CCGRx_CG5_MASK				(0x3 << 10)
480
#define MXC_CCM_CCGRx_CG4_MASK				(0x3 << 8)
481
#define MXC_CCM_CCGRx_CG3_MASK				(0x3 << 6)
482
#define MXC_CCM_CCGRx_CG2_MASK				(0x3 << 4)
483
#define MXC_CCM_CCGRx_CG1_MASK				(0x3 << 2)
484
#define MXC_CCM_CCGRx_CG0_MASK				(0x3 << 0)
485

486
#define MXC_CCM_CCGRx_CG15_OFFSET			30
487
#define MXC_CCM_CCGRx_CG14_OFFSET			28
488
#define MXC_CCM_CCGRx_CG13_OFFSET			26
489
#define MXC_CCM_CCGRx_CG12_OFFSET			24
490
#define MXC_CCM_CCGRx_CG11_OFFSET			22
491
#define MXC_CCM_CCGRx_CG10_OFFSET			20
492
#define MXC_CCM_CCGRx_CG9_OFFSET			18
493
#define MXC_CCM_CCGRx_CG8_OFFSET			16
494
#define MXC_CCM_CCGRx_CG7_OFFSET			14
495
#define MXC_CCM_CCGRx_CG6_OFFSET			12
496
#define MXC_CCM_CCGRx_CG5_OFFSET			10
497
#define MXC_CCM_CCGRx_CG4_OFFSET			8
498
#define MXC_CCM_CCGRx_CG3_OFFSET			6
499
#define MXC_CCM_CCGRx_CG2_OFFSET			4
500
#define MXC_CCM_CCGRx_CG1_OFFSET			2
501
#define MXC_CCM_CCGRx_CG0_OFFSET			0
502

503
#define MXC_DPTC_LP_BASE	(MX51_GPC_BASE + 0x80)
504
#define MXC_DPTC_GP_BASE	(MX51_GPC_BASE + 0x100)
505
#define MXC_DVFS_CORE_BASE	(MX51_GPC_BASE + 0x180)
506
#define MXC_DPTC_PER_BASE	(MX51_GPC_BASE + 0x1C0)
507
#define MXC_PGC_IPU_BASE	(MX51_GPC_BASE + 0x220)
508
#define MXC_PGC_VPU_BASE	(MX51_GPC_BASE + 0x240)
509
#define MXC_PGC_GPU_BASE	(MX51_GPC_BASE + 0x260)
510
#define MXC_SRPG_NEON_BASE	(MX51_GPC_BASE + 0x280)
511
#define MXC_SRPG_ARM_BASE	(MX51_GPC_BASE + 0x2A0)
512
#define MXC_SRPG_EMPGC0_BASE	(MX51_GPC_BASE + 0x2C0)
513
#define MXC_SRPG_EMPGC1_BASE	(MX51_GPC_BASE + 0x2D0)
514
#define MXC_SRPG_MEGAMIX_BASE	(MX51_GPC_BASE + 0x2E0)
515
#define MXC_SRPG_EMI_BASE	(MX51_GPC_BASE + 0x300)
516

517
/* CORTEXA8 platform */
518
#define MXC_CORTEXA8_PLAT_PVID		(MX51_CORTEXA8_BASE + 0x0)
519
#define MXC_CORTEXA8_PLAT_GPC		(MX51_CORTEXA8_BASE + 0x4)
520
#define MXC_CORTEXA8_PLAT_PIC		(MX51_CORTEXA8_BASE + 0x8)
521
#define MXC_CORTEXA8_PLAT_LPC		(MX51_CORTEXA8_BASE + 0xC)
522
#define MXC_CORTEXA8_PLAT_NEON_LPC	(MX51_CORTEXA8_BASE + 0x10)
523
#define MXC_CORTEXA8_PLAT_ICGC		(MX51_CORTEXA8_BASE + 0x14)
524
#define MXC_CORTEXA8_PLAT_AMC		(MX51_CORTEXA8_BASE + 0x18)
525
#define MXC_CORTEXA8_PLAT_NMC		(MX51_CORTEXA8_BASE + 0x20)
526
#define MXC_CORTEXA8_PLAT_NMS		(MX51_CORTEXA8_BASE + 0x24)
527

528
/* DVFS CORE */
529
#define MXC_DVFSTHRS		(MXC_DVFS_CORE_BASE + 0x00)
530
#define MXC_DVFSCOUN		(MXC_DVFS_CORE_BASE + 0x04)
531
#define MXC_DVFSSIG1		(MXC_DVFS_CORE_BASE + 0x08)
532
#define MXC_DVFSSIG0		(MXC_DVFS_CORE_BASE + 0x0C)
533
#define MXC_DVFSGPC0		(MXC_DVFS_CORE_BASE + 0x10)
534
#define MXC_DVFSGPC1		(MXC_DVFS_CORE_BASE + 0x14)
535
#define MXC_DVFSGPBT		(MXC_DVFS_CORE_BASE + 0x18)
536
#define MXC_DVFSEMAC		(MXC_DVFS_CORE_BASE + 0x1C)
537
#define MXC_DVFSCNTR		(MXC_DVFS_CORE_BASE + 0x20)
538
#define MXC_DVFSLTR0_0		(MXC_DVFS_CORE_BASE + 0x24)
539
#define MXC_DVFSLTR0_1		(MXC_DVFS_CORE_BASE + 0x28)
540
#define MXC_DVFSLTR1_0		(MXC_DVFS_CORE_BASE + 0x2C)
541
#define MXC_DVFSLTR1_1		(MXC_DVFS_CORE_BASE + 0x30)
542
#define MXC_DVFSPT0 		(MXC_DVFS_CORE_BASE + 0x34)
543
#define MXC_DVFSPT1 		(MXC_DVFS_CORE_BASE + 0x38)
544
#define MXC_DVFSPT2 		(MXC_DVFS_CORE_BASE + 0x3C)
545
#define MXC_DVFSPT3 		(MXC_DVFS_CORE_BASE + 0x40)
546

547
/* GPC */
548
#define MXC_GPC_CNTR		(MX51_GPC_BASE + 0x0)
549
#define MXC_GPC_PGR		(MX51_GPC_BASE + 0x4)
550
#define MXC_GPC_VCR		(MX51_GPC_BASE + 0x8)
551
#define MXC_GPC_ALL_PU		(MX51_GPC_BASE + 0xC)
552
#define MXC_GPC_NEON		(MX51_GPC_BASE + 0x10)
553
#define MXC_GPC_PGR_ARMPG_OFFSET	8
554
#define MXC_GPC_PGR_ARMPG_MASK		(3 << 8)
555

556
/* PGC */
557
#define MXC_PGC_IPU_PGCR	(MXC_PGC_IPU_BASE + 0x0)
558
#define MXC_PGC_IPU_PGSR	(MXC_PGC_IPU_BASE + 0xC)
559
#define MXC_PGC_VPU_PGCR	(MXC_PGC_VPU_BASE + 0x0)
560
#define MXC_PGC_VPU_PGSR	(MXC_PGC_VPU_BASE + 0xC)
561
#define MXC_PGC_GPU_PGCR	(MXC_PGC_GPU_BASE + 0x0)
562
#define MXC_PGC_GPU_PGSR	(MXC_PGC_GPU_BASE + 0xC)
563

564
#define MXC_PGCR_PCR		1
565
#define MXC_SRPGCR_PCR		1
566
#define MXC_EMPGCR_PCR		1
567
#define MXC_PGSR_PSR		1
568

569

570
#define MXC_CORTEXA8_PLAT_LPC_DSM	(1 << 0)
571
#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM	(1 << 1)
572

573
/* SRPG */
574
#define MXC_SRPG_NEON_SRPGCR	(MXC_SRPG_NEON_BASE + 0x0)
575
#define MXC_SRPG_NEON_PUPSCR	(MXC_SRPG_NEON_BASE + 0x4)
576
#define MXC_SRPG_NEON_PDNSCR	(MXC_SRPG_NEON_BASE + 0x8)
577

578
#define MXC_SRPG_ARM_SRPGCR	(MXC_SRPG_ARM_BASE + 0x0)
579
#define MXC_SRPG_ARM_PUPSCR	(MXC_SRPG_ARM_BASE + 0x4)
580
#define MXC_SRPG_ARM_PDNSCR	(MXC_SRPG_ARM_BASE + 0x8)
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582
#define MXC_SRPG_EMPGC0_SRPGCR	(MXC_SRPG_EMPGC0_BASE + 0x0)
583
#define MXC_SRPG_EMPGC0_PUPSCR	(MXC_SRPG_EMPGC0_BASE + 0x4)
584
#define MXC_SRPG_EMPGC0_PDNSCR	(MXC_SRPG_EMPGC0_BASE + 0x8)
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586
#define MXC_SRPG_EMPGC1_SRPGCR	(MXC_SRPG_EMPGC1_BASE + 0x0)
587
#define MXC_SRPG_EMPGC1_PUPSCR	(MXC_SRPG_EMPGC1_BASE + 0x4)
588
#define MXC_SRPG_EMPGC1_PDNSCR	(MXC_SRPG_EMPGC1_BASE + 0x8)
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590
#define MXC_SRPG_MEGAMIX_SRPGCR		(MXC_SRPG_MEGAMIX_BASE + 0x0)
591
#define MXC_SRPG_MEGAMIX_PUPSCR		(MXC_SRPG_MEGAMIX_BASE + 0x4)
592
#define MXC_SRPG_MEGAMIX_PDNSCR		(MXC_SRPG_MEGAMIX_BASE + 0x8)
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594
#define MXC_SRPGC_EMI_SRPGCR	(MXC_SRPGC_EMI_BASE + 0x0)
595
#define MXC_SRPGC_EMI_PUPSCR	(MXC_SRPGC_EMI_BASE + 0x4)
596
#define MXC_SRPGC_EMI_PDNSCR	(MXC_SRPGC_EMI_BASE + 0x8)
597

598
#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
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