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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-mx5/system.c
10817 views
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/*

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 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.

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 */

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/*

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 * The code contained herein is licensed under the GNU General Public

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 * License. You may obtain a copy of the GNU General Public License

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 * Version 2 or later at the following locations:

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 *

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 * http://www.opensource.org/licenses/gpl-license.html

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 * http://www.gnu.org/copyleft/gpl.html

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 */

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#include <linux/platform_device.h>

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#include <linux/io.h>

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#include <mach/hardware.h>

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#include "crm_regs.h"

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/* set cpu low power mode before WFI instruction. This function is called

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  * mx5 because it can be used for mx50, mx51, and mx53.*/

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void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)

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{

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	u32 plat_lpc, arm_srpgcr, ccm_clpcr;

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	u32 empgc0, empgc1;

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	int stop_mode = 0;

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	/* always allow platform to issue a deep sleep mode request */

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	plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &

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	    ~(MXC_CORTEXA8_PLAT_LPC_DSM);

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	ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);

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	arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);

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	empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);

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	empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);

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	switch (mode) {

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	case WAIT_CLOCKED:

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		break;

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	case WAIT_UNCLOCKED:

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		ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;

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		break;

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	case WAIT_UNCLOCKED_POWER_OFF:

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	case STOP_POWER_OFF:

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		plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM

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			    | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;

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		if (mode == WAIT_UNCLOCKED_POWER_OFF) {

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			ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;

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			ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;

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			ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;

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			stop_mode = 0;

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		} else {

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			ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;

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			ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;

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			ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;

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			ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;

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			stop_mode = 1;

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		}

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		arm_srpgcr |= MXC_SRPGCR_PCR;

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		if (tzic_enable_wake(1) != 0)

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			return;

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		break;

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	case STOP_POWER_ON:

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		ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;

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		break;

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	default:

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		printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);

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		return;

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	}

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	__raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);

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	__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);

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	__raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);

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	/* Enable NEON SRPG for all but MX50TO1.0. */

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	if (mx50_revision() != IMX_CHIP_REVISION_1_0)

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		__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);

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	if (stop_mode) {

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		empgc0 |= MXC_SRPGCR_PCR;

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		empgc1 |= MXC_SRPGCR_PCR;

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		__raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);

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		__raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);

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	}

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}

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