CoCalc -- regs-clkctrl-mx23.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/arm/mach-mxs/regs-clkctrl-mx23.h
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/*
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 * Freescale CLKCTRL Register Definitions
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 *
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 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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 * Copyright 2008-2010 Freescale Semiconductor, Inc.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
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 *
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 * This file is created by xml file. Don't Edit it.
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 *
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 * Xml Revision: 1.48
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 * Template revision: 26195
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 */
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#ifndef __REGS_CLKCTRL_MX23_H__
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#define __REGS_CLKCTRL_MX23_H__
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#define HW_CLKCTRL_PLLCTRL0	(0x00000000)
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#define HW_CLKCTRL_PLLCTRL0_SET	(0x00000004)
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#define HW_CLKCTRL_PLLCTRL0_CLR	(0x00000008)
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#define HW_CLKCTRL_PLLCTRL0_TOG	(0x0000000c)
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#define BP_CLKCTRL_PLLCTRL0_LFR_SEL	28
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#define BM_CLKCTRL_PLLCTRL0_LFR_SEL	0x30000000
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#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)  \
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		(((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
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#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT   0x0
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#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2   0x1
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#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05  0x2
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#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
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#define BP_CLKCTRL_PLLCTRL0_CP_SEL	24
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#define BM_CLKCTRL_PLLCTRL0_CP_SEL	0x03000000
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#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)  \
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		(((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
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#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT   0x0
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#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2   0x1
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#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05  0x2
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#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
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#define BP_CLKCTRL_PLLCTRL0_DIV_SEL	20
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#define BM_CLKCTRL_PLLCTRL0_DIV_SEL	0x00300000
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#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)  \
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		(((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
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#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT   0x0
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#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER     0x1
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#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST    0x2
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#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
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#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS	0x00040000
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#define BM_CLKCTRL_PLLCTRL0_POWER	0x00010000
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#define HW_CLKCTRL_PLLCTRL1	(0x00000010)
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#define BM_CLKCTRL_PLLCTRL1_LOCK	0x80000000
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#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK	0x40000000
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#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT	0
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#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT	0x0000FFFF
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#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)  \
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		(((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
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#define HW_CLKCTRL_CPU	(0x00000020)
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#define HW_CLKCTRL_CPU_SET	(0x00000024)
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#define HW_CLKCTRL_CPU_CLR	(0x00000028)
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#define HW_CLKCTRL_CPU_TOG	(0x0000002c)
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#define BM_CLKCTRL_CPU_BUSY_REF_XTAL	0x20000000
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#define BM_CLKCTRL_CPU_BUSY_REF_CPU	0x10000000
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#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN	0x04000000
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#define BP_CLKCTRL_CPU_DIV_XTAL	16
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#define BM_CLKCTRL_CPU_DIV_XTAL	0x03FF0000
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#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
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		(((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
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#define BM_CLKCTRL_CPU_INTERRUPT_WAIT	0x00001000
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#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN	0x00000400
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#define BP_CLKCTRL_CPU_DIV_CPU	0
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#define BM_CLKCTRL_CPU_DIV_CPU	0x0000003F
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#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
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		(((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
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#define HW_CLKCTRL_HBUS	(0x00000030)
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#define HW_CLKCTRL_HBUS_SET	(0x00000034)
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#define HW_CLKCTRL_HBUS_CLR	(0x00000038)
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#define HW_CLKCTRL_HBUS_TOG	(0x0000003c)
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#define BM_CLKCTRL_HBUS_BUSY	0x20000000
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#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE	0x10000000
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#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE	0x08000000
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#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE	0x04000000
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#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE	0x02000000
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#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	0x01000000
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#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE	0x00800000
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#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE	0x00400000
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#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	0x00200000
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#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE	0x00100000
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#define BP_CLKCTRL_HBUS_SLOW_DIV	16
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#define BM_CLKCTRL_HBUS_SLOW_DIV	0x00070000
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#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
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		(((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
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#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
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#define BM_CLKCTRL_HBUS_DIV_FRAC_EN	0x00000020
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#define BP_CLKCTRL_HBUS_DIV	0
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#define BM_CLKCTRL_HBUS_DIV	0x0000001F
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#define BF_CLKCTRL_HBUS_DIV(v)  \
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		(((v) << 0) & BM_CLKCTRL_HBUS_DIV)
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#define HW_CLKCTRL_XBUS	(0x00000040)
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#define BM_CLKCTRL_XBUS_BUSY	0x80000000
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#define BM_CLKCTRL_XBUS_DIV_FRAC_EN	0x00000400
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#define BP_CLKCTRL_XBUS_DIV	0
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#define BM_CLKCTRL_XBUS_DIV	0x000003FF
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#define BF_CLKCTRL_XBUS_DIV(v)  \
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		(((v) << 0) & BM_CLKCTRL_XBUS_DIV)
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#define HW_CLKCTRL_XTAL	(0x00000050)
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#define HW_CLKCTRL_XTAL_SET	(0x00000054)
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#define HW_CLKCTRL_XTAL_CLR	(0x00000058)
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#define HW_CLKCTRL_XTAL_TOG	(0x0000005c)
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#define BP_CLKCTRL_XTAL_UART_CLK_GATE	31
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#define BM_CLKCTRL_XTAL_UART_CLK_GATE	0x80000000
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#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE	30
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#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE	0x40000000
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#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE	29
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#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE	0x20000000
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#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE	0x10000000
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#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE	0x08000000
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#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE	26
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#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE	0x04000000
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#define BP_CLKCTRL_XTAL_DIV_UART	0
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#define BM_CLKCTRL_XTAL_DIV_UART	0x00000003
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#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
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		(((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
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#define HW_CLKCTRL_PIX	(0x00000060)
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#define BP_CLKCTRL_PIX_CLKGATE	31
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#define BM_CLKCTRL_PIX_CLKGATE	0x80000000
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#define BM_CLKCTRL_PIX_BUSY	0x20000000
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#define BM_CLKCTRL_PIX_DIV_FRAC_EN	0x00001000
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#define BP_CLKCTRL_PIX_DIV	0
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#define BM_CLKCTRL_PIX_DIV	0x00000FFF
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#define BF_CLKCTRL_PIX_DIV(v)  \
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		(((v) << 0) & BM_CLKCTRL_PIX_DIV)
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#define HW_CLKCTRL_SSP	(0x00000070)
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#define BP_CLKCTRL_SSP_CLKGATE	31
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#define BM_CLKCTRL_SSP_CLKGATE	0x80000000
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#define BM_CLKCTRL_SSP_BUSY	0x20000000
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#define BM_CLKCTRL_SSP_DIV_FRAC_EN	0x00000200
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#define BP_CLKCTRL_SSP_DIV	0
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#define BM_CLKCTRL_SSP_DIV	0x000001FF
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#define BF_CLKCTRL_SSP_DIV(v)  \
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		(((v) << 0) & BM_CLKCTRL_SSP_DIV)
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#define HW_CLKCTRL_GPMI	(0x00000080)
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#define BP_CLKCTRL_GPMI_CLKGATE	31
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#define BM_CLKCTRL_GPMI_CLKGATE	0x80000000
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#define BM_CLKCTRL_GPMI_BUSY	0x20000000
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#define BM_CLKCTRL_GPMI_DIV_FRAC_EN	0x00000400
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#define BP_CLKCTRL_GPMI_DIV	0
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#define BM_CLKCTRL_GPMI_DIV	0x000003FF
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#define BF_CLKCTRL_GPMI_DIV(v)  \
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		(((v) << 0) & BM_CLKCTRL_GPMI_DIV)
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#define HW_CLKCTRL_SPDIF	(0x00000090)
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#define BM_CLKCTRL_SPDIF_CLKGATE	0x80000000
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#define HW_CLKCTRL_EMI	(0x000000a0)
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#define BP_CLKCTRL_EMI_CLKGATE	31
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#define BM_CLKCTRL_EMI_CLKGATE	0x80000000
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#define BM_CLKCTRL_EMI_SYNC_MODE_EN	0x40000000
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#define BM_CLKCTRL_EMI_BUSY_REF_XTAL	0x20000000
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#define BM_CLKCTRL_EMI_BUSY_REF_EMI	0x10000000
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#define BM_CLKCTRL_EMI_BUSY_REF_CPU	0x08000000
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#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE	0x04000000
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#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC	0x00020000
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#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE	0x00010000
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#define BP_CLKCTRL_EMI_DIV_XTAL	8
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#define BM_CLKCTRL_EMI_DIV_XTAL	0x00000F00
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#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
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		(((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
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#define BP_CLKCTRL_EMI_DIV_EMI	0
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#define BM_CLKCTRL_EMI_DIV_EMI	0x0000003F
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#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
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		(((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
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#define HW_CLKCTRL_IR	(0x000000b0)
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#define BM_CLKCTRL_IR_CLKGATE	0x80000000
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#define BM_CLKCTRL_IR_AUTO_DIV	0x20000000
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#define BM_CLKCTRL_IR_IR_BUSY	0x10000000
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#define BM_CLKCTRL_IR_IROV_BUSY	0x08000000
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#define BP_CLKCTRL_IR_IROV_DIV	16
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#define BM_CLKCTRL_IR_IROV_DIV	0x01FF0000
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#define BF_CLKCTRL_IR_IROV_DIV(v)  \
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		(((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
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#define BP_CLKCTRL_IR_IR_DIV	0
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#define BM_CLKCTRL_IR_IR_DIV	0x000003FF
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#define BF_CLKCTRL_IR_IR_DIV(v)  \
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		(((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
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#define HW_CLKCTRL_SAIF	(0x000000c0)
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#define BM_CLKCTRL_SAIF_CLKGATE	0x80000000
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#define BM_CLKCTRL_SAIF_BUSY	0x20000000
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#define BM_CLKCTRL_SAIF_DIV_FRAC_EN	0x00010000
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#define BP_CLKCTRL_SAIF_DIV	0
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#define BM_CLKCTRL_SAIF_DIV	0x0000FFFF
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#define BF_CLKCTRL_SAIF_DIV(v)  \
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		(((v) << 0) & BM_CLKCTRL_SAIF_DIV)
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#define HW_CLKCTRL_TV	(0x000000d0)
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#define BM_CLKCTRL_TV_CLK_TV108M_GATE	0x80000000
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#define BM_CLKCTRL_TV_CLK_TV_GATE	0x40000000
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#define HW_CLKCTRL_ETM	(0x000000e0)
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#define BM_CLKCTRL_ETM_CLKGATE	0x80000000
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#define BM_CLKCTRL_ETM_BUSY	0x20000000
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#define BM_CLKCTRL_ETM_DIV_FRAC_EN	0x00000040
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#define BP_CLKCTRL_ETM_DIV	0
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#define BM_CLKCTRL_ETM_DIV	0x0000003F
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#define BF_CLKCTRL_ETM_DIV(v)  \
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		(((v) << 0) & BM_CLKCTRL_ETM_DIV)
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#define HW_CLKCTRL_FRAC	(0x000000f0)
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#define HW_CLKCTRL_FRAC_SET	(0x000000f4)
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#define HW_CLKCTRL_FRAC_CLR	(0x000000f8)
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#define HW_CLKCTRL_FRAC_TOG	(0x000000fc)
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#define BP_CLKCTRL_FRAC_CLKGATEIO	31
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#define BM_CLKCTRL_FRAC_CLKGATEIO	0x80000000
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#define BM_CLKCTRL_FRAC_IO_STABLE	0x40000000
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#define BP_CLKCTRL_FRAC_IOFRAC	24
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#define BM_CLKCTRL_FRAC_IOFRAC	0x3F000000
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#define BF_CLKCTRL_FRAC_IOFRAC(v)  \
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		(((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
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#define BP_CLKCTRL_FRAC_CLKGATEPIX	23
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#define BM_CLKCTRL_FRAC_CLKGATEPIX	0x00800000
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#define BM_CLKCTRL_FRAC_PIX_STABLE	0x00400000
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#define BP_CLKCTRL_FRAC_PIXFRAC	16
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#define BM_CLKCTRL_FRAC_PIXFRAC	0x003F0000
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#define BF_CLKCTRL_FRAC_PIXFRAC(v)  \
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		(((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
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#define BP_CLKCTRL_FRAC_CLKGATEEMI	15
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#define BM_CLKCTRL_FRAC_CLKGATEEMI	0x00008000
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#define BM_CLKCTRL_FRAC_EMI_STABLE	0x00004000
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#define BP_CLKCTRL_FRAC_EMIFRAC	8
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#define BM_CLKCTRL_FRAC_EMIFRAC	0x00003F00
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#define BF_CLKCTRL_FRAC_EMIFRAC(v)  \
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		(((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
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#define BP_CLKCTRL_FRAC_CLKGATECPU	7
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#define BM_CLKCTRL_FRAC_CLKGATECPU	0x00000080
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#define BM_CLKCTRL_FRAC_CPU_STABLE	0x00000040
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#define BP_CLKCTRL_FRAC_CPUFRAC	0
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#define BM_CLKCTRL_FRAC_CPUFRAC	0x0000003F
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#define BF_CLKCTRL_FRAC_CPUFRAC(v)  \
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		(((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
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#define HW_CLKCTRL_FRAC1	(0x00000100)
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#define HW_CLKCTRL_FRAC1_SET	(0x00000104)
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#define HW_CLKCTRL_FRAC1_CLR	(0x00000108)
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#define HW_CLKCTRL_FRAC1_TOG	(0x0000010c)
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#define BM_CLKCTRL_FRAC1_CLKGATEVID	0x80000000
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#define BM_CLKCTRL_FRAC1_VID_STABLE	0x40000000
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#define HW_CLKCTRL_CLKSEQ	(0x00000110)
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#define HW_CLKCTRL_CLKSEQ_SET	(0x00000114)
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#define HW_CLKCTRL_CLKSEQ_CLR	(0x00000118)
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#define HW_CLKCTRL_CLKSEQ_TOG	(0x0000011c)
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#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM	0x00000100
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#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU	0x00000080
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#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI	0x00000040
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#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP	0x00000020
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#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI	0x00000010
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#define BM_CLKCTRL_CLKSEQ_BYPASS_IR	0x00000008
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#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX	0x00000002
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#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF	0x00000001
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#define HW_CLKCTRL_RESET	(0x00000120)
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#define BM_CLKCTRL_RESET_CHIP	0x00000002
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#define BM_CLKCTRL_RESET_DIG	0x00000001
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#define HW_CLKCTRL_STATUS	(0x00000130)
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#define BP_CLKCTRL_STATUS_CPU_LIMIT	30
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#define BM_CLKCTRL_STATUS_CPU_LIMIT	0xC0000000
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#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
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		(((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
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#define HW_CLKCTRL_VERSION	(0x00000140)
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#define BP_CLKCTRL_VERSION_MAJOR	24
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#define BM_CLKCTRL_VERSION_MAJOR	0xFF000000
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#define BF_CLKCTRL_VERSION_MAJOR(v) \
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		(((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
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#define BP_CLKCTRL_VERSION_MINOR	16
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#define BM_CLKCTRL_VERSION_MINOR	0x00FF0000
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#define BF_CLKCTRL_VERSION_MINOR(v)  \
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		(((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
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#define BP_CLKCTRL_VERSION_STEP	0
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#define BM_CLKCTRL_VERSION_STEP	0x0000FFFF
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#define BF_CLKCTRL_VERSION_STEP(v)  \
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		(((v) << 0) & BM_CLKCTRL_VERSION_STEP)
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#endif /* __REGS_CLKCTRL_MX23_H__ */
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