CoCalc -- irqs.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/arm/mach-pnx4008/include/mach/irqs.h
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/*
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 * arch/arm/mach-pnx4008/include/mach/irqs.h
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 *
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 * PNX4008 IRQ controller driver - header file
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 *
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 * Author: Dmitry Chigirev <[email protected]>
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 *
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 * 2005 (c) MontaVista Software, Inc. This file is licensed under
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 * the terms of the GNU General Public License version 2. This program
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 * is licensed "as is" without any warranty of any kind, whether express
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 * or implied.
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 */
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#ifndef __PNX4008_IRQS_h__
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#define __PNX4008_IRQS_h__
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#define NR_IRQS         96
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/*Manual: table 259, page 199*/
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/*SUB2 Interrupt Routing (SIC2)*/
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#define SIC2_BASE_INT   64
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#define CLK_SWITCH_ARM_INT 95	/*manual: Clkswitch ARM  */
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#define CLK_SWITCH_DSP_INT 94	/*manual: ClkSwitch DSP  */
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#define CLK_SWITCH_AUD_INT 93	/*manual: Clkswitch AUD  */
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#define GPI_06_INT         92
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#define GPI_05_INT         91
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#define GPI_04_INT         90
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#define GPI_03_INT         89
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#define GPI_02_INT         88
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#define GPI_01_INT         87
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#define GPI_00_INT         86
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#define BT_CLKREQ_INT      85
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#define SPI1_DATIN_INT     84
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#define U5_RX_INT          83
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#define SDIO_INT_N         82
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#define CAM_HS_INT         81
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#define CAM_VS_INT         80
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#define GPI_07_INT         79
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#define DISP_SYNC_INT      78
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#define DSP_INT8           77
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#define U7_HCTS_INT        76
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#define GPI_10_INT         75
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#define GPI_09_INT         74
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#define GPI_08_INT         73
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#define DSP_INT7           72
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#define U2_HCTS_INT        71
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#define SPI2_DATIN_INT     70
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#define GPIO_05_INT        69
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#define GPIO_04_INT        68
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#define GPIO_03_INT        67
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#define GPIO_02_INT        66
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#define GPIO_01_INT        65
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#define GPIO_00_INT        64
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/*Manual: table 258, page 198*/
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/*SUB1 Interrupt Routing (SIC1)*/
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#define SIC1_BASE_INT   32
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#define USB_I2C_INT        63
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#define USB_DEV_HP_INT     62
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#define USB_DEV_LP_INT     61
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#define USB_DEV_DMA_INT    60
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#define USB_HOST_INT       59
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#define USB_OTG_ATX_INT_N  58
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#define USB_OTG_TIMER_INT  57
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#define SW_INT             56
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#define SPI1_INT           55
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#define KEY_IRQ            54
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#define DSP_M_INT          53
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#define RTC_INT            52
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#define I2C_1_INT          51
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#define I2C_2_INT          50
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#define PLL1_LOCK_INT      49
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#define PLL2_LOCK_INT      48
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#define PLL3_LOCK_INT      47
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#define PLL4_LOCK_INT      46
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#define PLL5_LOCK_INT      45
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#define SPI2_INT           44
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#define DSP_INT1           43
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#define DSP_INT2           42
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#define DSP_TDM_INT2       41
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#define TS_AUX_INT         40
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#define TS_IRQ             39
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#define TS_P_INT           38
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#define UOUT1_TO_PAD_INT   37
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#define GPI_11_INT         36
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#define DSP_INT4           35
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#define JTAG_COMM_RX_INT   34
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#define JTAG_COMM_TX_INT   33
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#define DSP_INT3           32
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/*Manual: table 257, page 197*/
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/*MAIN Interrupt Routing*/
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#define MAIN_BASE_INT   0
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#define SUB2_FIQ_N         31	/*active low */
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#define SUB1_FIQ_N         30	/*active low */
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#define JPEG_INT           29
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#define DMA_INT            28
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#define MSTIMER_INT        27
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#define IIR1_INT           26
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#define IIR2_INT           25
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#define IIR7_INT           24
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#define DSP_TDM_INT0       23
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#define DSP_TDM_INT1       22
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#define DSP_P_INT          21
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#define DSP_INT0           20
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#define DUM_INT            19
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#define UOUT0_TO_PAD_INT   18
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#define MP4_ENC_INT        17
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#define MP4_DEC_INT        16
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#define SD0_INT            15
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#define MBX_INT            14
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#define SD1_INT            13
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#define MS_INT_N           12
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#define FLASH_INT          11 /*NAND*/
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#define IIR6_INT           10
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#define IIR5_INT           9
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#define IIR4_INT           8
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#define IIR3_INT           7
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#define WATCH_INT          6
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#define HSTIMER_INT        5
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#define ARCH_TIMER_IRQ     HSTIMER_INT
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#define CAM_INT            4
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#define PRNG_INT           3
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#define CRYPTO_INT         2
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#define SUB2_IRQ_N         1	/*active low */
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#define SUB1_IRQ_N         0	/*active low */
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#define PNX4008_IRQ_TYPES \
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{                                           /*IRQ #'s: */         \
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IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /*  0, 1, 2, 3 */     \
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IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  4, 5, 6, 7 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /*  8, 9,10,11 */     \
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IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 28,29,30,31 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */  \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_LOW,  /* 48,49,50,51 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW,  IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */     \
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IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */     \
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}
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/* Start Enable Pin Interrupts - table 58 page 66 */
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#define SE_PIN_BASE_INT   32
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#define SE_U7_RX_INT            63
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#define SE_U7_HCTS_INT          62
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#define SE_BT_CLKREQ_INT        61
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#define SE_U6_IRRX_INT          60
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/*59 unused*/
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#define SE_U5_RX_INT            58
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#define SE_GPI_11_INT           57
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#define SE_U3_RX_INT            56
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#define SE_U2_HCTS_INT          55
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#define SE_U2_RX_INT            54
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#define SE_U1_RX_INT            53
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#define SE_DISP_SYNC_INT        52
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/*51 unused*/
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#define SE_SDIO_INT_N           50
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#define SE_MSDIO_START_INT      49
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#define SE_GPI_06_INT           48
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#define SE_GPI_05_INT           47
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#define SE_GPI_04_INT           46
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#define SE_GPI_03_INT           45
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#define SE_GPI_02_INT           44
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#define SE_GPI_01_INT           43
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#define SE_GPI_00_INT           42
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#define SE_SYSCLKEN_PIN_INT     41
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#define SE_SPI1_DATAIN_INT      40
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#define SE_GPI_07_INT           39
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#define SE_SPI2_DATAIN_INT      38
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#define SE_GPI_10_INT           37
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#define SE_GPI_09_INT           36
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#define SE_GPI_08_INT           35
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/*34-32 unused*/
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/* Start Enable Internal Interrupts - table 57 page 65 */
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#define SE_INT_BASE_INT   0
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#define SE_TS_IRQ               31
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#define SE_TS_P_INT             30
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#define SE_TS_AUX_INT           29
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/*27-28 unused*/
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#define SE_USB_AHB_NEED_CLK_INT 26
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#define SE_MSTIMER_INT          25
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#define SE_RTC_INT              24
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#define SE_USB_NEED_CLK_INT     23
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#define SE_USB_INT              22
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#define SE_USB_I2C_INT          21
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#define SE_USB_OTG_TIMER_INT    20
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#endif /* __PNX4008_IRQS_h__ */
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