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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-pnx4008/time.h
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/*

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 * arch/arm/mach-pnx4008/include/mach/timex.h

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 *

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 * PNX4008 timers header file

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 *

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 * Author: Dmitry Chigirev <[email protected]>

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 *

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 * 2005 (c) MontaVista Software, Inc. This file is licensed under

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 * the terms of the GNU General Public License version 2. This program

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 * is licensed "as is" without any warranty of any kind, whether express

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 * or implied.

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 */

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#ifndef PNX_TIME_H

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#define PNX_TIME_H

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#include <linux/io.h>

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#include <mach/hardware.h>

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#define TICKS2USECS(x)	(x)

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/* MilliSecond Timer - Chapter 21 Page 202 */

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#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))

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#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))

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#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))

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#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))

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#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))

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#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))

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/* High Speed Timer - Chpater 22, Page 205 */

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#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))

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#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))

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#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))

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#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))

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#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))

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#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))

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#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))

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#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))

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#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))

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#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))

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#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))

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#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))

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/* IMPORTANT: both timers are UPCOUNTING */

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/* xSTIM_MCTRL bit definitions */

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#define MR0_INT        1

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#define RESET_COUNT0   (1<<1)

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#define STOP_COUNT0    (1<<2)

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#define MR1_INT        (1<<3)

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#define RESET_COUNT1   (1<<4)

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#define STOP_COUNT1    (1<<5)

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#define MR2_INT        (1<<6)

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#define RESET_COUNT2   (1<<7)

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#define STOP_COUNT2    (1<<8)

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/* xSTIM_CTRL bit definitions */

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#define COUNT_ENAB     1

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#define RESET_COUNT    (1<<1)

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#define DEBUG_EN       (1<<2)

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/* xSTIM_INT bit definitions */

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#define MATCH0_INT     1

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#define MATCH1_INT     (1<<1)

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#define MATCH2_INT     (1<<2)

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#define RTC_TICK0      (1<<4)

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#define RTC_TICK1      (1<<5)

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#endif

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