Path: blob/master/arch/arm/mach-realview/include/mach/board-pb1176.h
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/*1* arch/arm/mach-realview/include/mach/board-pb1176.h2*3* Copyright (C) 2008 ARM Limited4*5* This program is free software; you can redistribute it and/or modify6* it under the terms of the GNU General Public License version 2 as7* published by the Free Software Foundation.8*9* This program is distributed in the hope that it will be useful,10* but WITHOUT ANY WARRANTY; without even the implied warranty of11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the12* GNU General Public License for more details.13*14* You should have received a copy of the GNU General Public License15* along with this program; if not, write to the Free Software16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,17* MA 02110-1301, USA.18*/1920#ifndef __ASM_ARCH_BOARD_PB1176_H21#define __ASM_ARCH_BOARD_PB1176_H2223#include <mach/platform.h>2425/*26* Peripheral addresses27*/28#define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */29#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */30#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */31#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */32#define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */33#define REALVIEW_PB1176_FLASH_BASE 0x3000000034#define REALVIEW_PB1176_FLASH_SIZE SZ_64M35#define REALVIEW_PB1176_SEC_FLASH_BASE 0x3C000000 /* Secure flash */36#define REALVIEW_PB1176_SEC_FLASH_SIZE SZ_64M3738#define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */39#define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */40#define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */41#define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */42#define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */43#define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */44#define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */45#define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */46#define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */47#define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */48#define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */49#define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */50#define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */51#define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */5253/*54* PCI regions55*/56#define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */57#define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */58#define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */59#define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */60#define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */61#define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */6263#define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */64#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */65#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */66#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */67#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */68#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */6970#define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */71#define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */72#define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */73#define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */74#define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */7576/*77* Control register SYS_RESETCTL Bit 8 is set to 1 to force a soft reset78*/79#define REALVIEW_PB1176_SYS_SOFT_RESET 0x01008081#endif /* __ASM_ARCH_BOARD_PB1176_H */828384