Path: blob/master/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
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/*1* Pin definitions for AT32AP7000.2*3* Copyright (C) 2006 Atmel Corporation4*5* This program is free software; you can redistribute it and/or modify6* it under the terms of the GNU General Public License version 2 as7* published by the Free Software Foundation.8*/9#ifndef __ASM_ARCH_AT32AP700X_H__10#define __ASM_ARCH_AT32AP700X_H__1112#define GPIO_PERIPH_A 013#define GPIO_PERIPH_B 11415/*16* Pin numbers identifying specific GPIO pins on the chip. They can17* also be converted to IRQ numbers by passing them through18* gpio_to_irq().19*/20#define GPIO_PIOA_BASE (0)21#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)22#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)23#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)24#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)2526#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))27#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))28#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))29#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))30#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))313233/*34* DMAC peripheral hardware handshaking interfaces, used with dw_dmac35*/36#define DMAC_MCI_RX 037#define DMAC_MCI_TX 138#define DMAC_DAC_TX 239#define DMAC_AC97_A_RX 340#define DMAC_AC97_A_TX 441#define DMAC_AC97_B_RX 542#define DMAC_AC97_B_TX 643#define DMAC_DMAREQ_0 744#define DMAC_DMAREQ_1 845#define DMAC_DMAREQ_2 946#define DMAC_DMAREQ_3 104748/* HSB master IDs */49#define HMATRIX_MASTER_CPU_DCACHE 050#define HMATRIX_MASTER_CPU_ICACHE 151#define HMATRIX_MASTER_PDC 252#define HMATRIX_MASTER_ISI 353#define HMATRIX_MASTER_USBA 454#define HMATRIX_MASTER_LCDC 555#define HMATRIX_MASTER_MACB0 656#define HMATRIX_MASTER_MACB1 757#define HMATRIX_MASTER_DMACA_M0 858#define HMATRIX_MASTER_DMACA_M1 95960/* HSB slave IDs */61#define HMATRIX_SLAVE_SRAM0 062#define HMATRIX_SLAVE_SRAM1 163#define HMATRIX_SLAVE_PBA 264#define HMATRIX_SLAVE_PBB 365#define HMATRIX_SLAVE_EBI 466#define HMATRIX_SLAVE_USBA 567#define HMATRIX_SLAVE_LCDC 668#define HMATRIX_SLAVE_DMACA 76970/* Bits in HMATRIX SFR4 (EBI) */71#define HMATRIX_EBI_SDRAM_ENABLE (1 << 1)72#define HMATRIX_EBI_NAND_ENABLE (1 << 3)73#define HMATRIX_EBI_CF0_ENABLE (1 << 4)74#define HMATRIX_EBI_CF1_ENABLE (1 << 5)75#define HMATRIX_EBI_PULLUP_DISABLE (1 << 8)7677/*78* Base addresses of controllers that may be accessed early by79* platform code.80*/81#define PM_BASE 0xfff0000082#define HMATRIX_BASE 0xfff0080083#define SDRAMC_BASE 0xfff038008485/* LCDC on port C */86#define ATMEL_LCDC_PC_CC (1ULL << 19)87#define ATMEL_LCDC_PC_HSYNC (1ULL << 20)88#define ATMEL_LCDC_PC_PCLK (1ULL << 21)89#define ATMEL_LCDC_PC_VSYNC (1ULL << 22)90#define ATMEL_LCDC_PC_DVAL (1ULL << 23)91#define ATMEL_LCDC_PC_MODE (1ULL << 24)92#define ATMEL_LCDC_PC_PWR (1ULL << 25)93#define ATMEL_LCDC_PC_DATA0 (1ULL << 26)94#define ATMEL_LCDC_PC_DATA1 (1ULL << 27)95#define ATMEL_LCDC_PC_DATA2 (1ULL << 28)96#define ATMEL_LCDC_PC_DATA3 (1ULL << 29)97#define ATMEL_LCDC_PC_DATA4 (1ULL << 30)98#define ATMEL_LCDC_PC_DATA5 (1ULL << 31)99100/* LCDC on port D */101#define ATMEL_LCDC_PD_DATA6 (1ULL << 0)102#define ATMEL_LCDC_PD_DATA7 (1ULL << 1)103#define ATMEL_LCDC_PD_DATA8 (1ULL << 2)104#define ATMEL_LCDC_PD_DATA9 (1ULL << 3)105#define ATMEL_LCDC_PD_DATA10 (1ULL << 4)106#define ATMEL_LCDC_PD_DATA11 (1ULL << 5)107#define ATMEL_LCDC_PD_DATA12 (1ULL << 6)108#define ATMEL_LCDC_PD_DATA13 (1ULL << 7)109#define ATMEL_LCDC_PD_DATA14 (1ULL << 8)110#define ATMEL_LCDC_PD_DATA15 (1ULL << 9)111#define ATMEL_LCDC_PD_DATA16 (1ULL << 10)112#define ATMEL_LCDC_PD_DATA17 (1ULL << 11)113#define ATMEL_LCDC_PD_DATA18 (1ULL << 12)114#define ATMEL_LCDC_PD_DATA19 (1ULL << 13)115#define ATMEL_LCDC_PD_DATA20 (1ULL << 14)116#define ATMEL_LCDC_PD_DATA21 (1ULL << 15)117#define ATMEL_LCDC_PD_DATA22 (1ULL << 16)118#define ATMEL_LCDC_PD_DATA23 (1ULL << 17)119120/* LCDC on port E */121#define ATMEL_LCDC_PE_CC (1ULL << (32 + 0))122#define ATMEL_LCDC_PE_DVAL (1ULL << (32 + 1))123#define ATMEL_LCDC_PE_MODE (1ULL << (32 + 2))124#define ATMEL_LCDC_PE_DATA0 (1ULL << (32 + 3))125#define ATMEL_LCDC_PE_DATA1 (1ULL << (32 + 4))126#define ATMEL_LCDC_PE_DATA2 (1ULL << (32 + 5))127#define ATMEL_LCDC_PE_DATA3 (1ULL << (32 + 6))128#define ATMEL_LCDC_PE_DATA4 (1ULL << (32 + 7))129#define ATMEL_LCDC_PE_DATA8 (1ULL << (32 + 8))130#define ATMEL_LCDC_PE_DATA9 (1ULL << (32 + 9))131#define ATMEL_LCDC_PE_DATA10 (1ULL << (32 + 10))132#define ATMEL_LCDC_PE_DATA11 (1ULL << (32 + 11))133#define ATMEL_LCDC_PE_DATA12 (1ULL << (32 + 12))134#define ATMEL_LCDC_PE_DATA16 (1ULL << (32 + 13))135#define ATMEL_LCDC_PE_DATA17 (1ULL << (32 + 14))136#define ATMEL_LCDC_PE_DATA18 (1ULL << (32 + 15))137#define ATMEL_LCDC_PE_DATA19 (1ULL << (32 + 16))138#define ATMEL_LCDC_PE_DATA20 (1ULL << (32 + 17))139#define ATMEL_LCDC_PE_DATA21 (1ULL << (32 + 18))140141142#define ATMEL_LCDC(PORT, PIN) (ATMEL_LCDC_##PORT##_##PIN)143144145#define ATMEL_LCDC_PRI_24B_DATA ( \146ATMEL_LCDC(PC, DATA0) | ATMEL_LCDC(PC, DATA1) | \147ATMEL_LCDC(PC, DATA2) | ATMEL_LCDC(PC, DATA3) | \148ATMEL_LCDC(PC, DATA4) | ATMEL_LCDC(PC, DATA5) | \149ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \150ATMEL_LCDC(PD, DATA8) | ATMEL_LCDC(PD, DATA9) | \151ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) | \152ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) | \153ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \154ATMEL_LCDC(PD, DATA16) | ATMEL_LCDC(PD, DATA17) | \155ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) | \156ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) | \157ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))158159#define ATMEL_LCDC_ALT_24B_DATA ( \160ATMEL_LCDC(PE, DATA0) | ATMEL_LCDC(PE, DATA1) | \161ATMEL_LCDC(PE, DATA2) | ATMEL_LCDC(PE, DATA3) | \162ATMEL_LCDC(PE, DATA4) | ATMEL_LCDC(PC, DATA5) | \163ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \164ATMEL_LCDC(PE, DATA8) | ATMEL_LCDC(PE, DATA9) | \165ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) | \166ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) | \167ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \168ATMEL_LCDC(PE, DATA16) | ATMEL_LCDC(PE, DATA17) | \169ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) | \170ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) | \171ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))172173#define ATMEL_LCDC_PRI_18B_DATA ( \174ATMEL_LCDC(PC, DATA2) | ATMEL_LCDC(PC, DATA3) | \175ATMEL_LCDC(PC, DATA4) | ATMEL_LCDC(PC, DATA5) | \176ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \177ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) | \178ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) | \179ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \180ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) | \181ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) | \182ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))183184#define ATMEL_LCDC_ALT_18B_DATA ( \185ATMEL_LCDC(PE, DATA2) | ATMEL_LCDC(PE, DATA3) | \186ATMEL_LCDC(PE, DATA4) | ATMEL_LCDC(PC, DATA5) | \187ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \188ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) | \189ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) | \190ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \191ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) | \192ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) | \193ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))194195#define ATMEL_LCDC_PRI_15B_DATA ( \196ATMEL_LCDC(PC, DATA3) | ATMEL_LCDC(PC, DATA4) | \197ATMEL_LCDC(PC, DATA5) | ATMEL_LCDC(PD, DATA6) | \198ATMEL_LCDC(PD, DATA7) | \199ATMEL_LCDC(PD, DATA11) | ATMEL_LCDC(PD, DATA12) | \200ATMEL_LCDC(PD, DATA13) | ATMEL_LCDC(PD, DATA14) | \201ATMEL_LCDC(PD, DATA15) | \202ATMEL_LCDC(PD, DATA19) | ATMEL_LCDC(PD, DATA20) | \203ATMEL_LCDC(PD, DATA21) | ATMEL_LCDC(PD, DATA22) | \204ATMEL_LCDC(PD, DATA23))205206#define ATMEL_LCDC_ALT_15B_DATA ( \207ATMEL_LCDC(PE, DATA3) | ATMEL_LCDC(PE, DATA4) | \208ATMEL_LCDC(PC, DATA5) | ATMEL_LCDC(PD, DATA6) | \209ATMEL_LCDC(PD, DATA7) | \210ATMEL_LCDC(PE, DATA11) | ATMEL_LCDC(PE, DATA12) | \211ATMEL_LCDC(PD, DATA13) | ATMEL_LCDC(PD, DATA14) | \212ATMEL_LCDC(PD, DATA15) | \213ATMEL_LCDC(PE, DATA19) | ATMEL_LCDC(PE, DATA20) | \214ATMEL_LCDC(PE, DATA21) | ATMEL_LCDC(PD, DATA22) | \215ATMEL_LCDC(PD, DATA23))216217#define ATMEL_LCDC_PRI_CONTROL ( \218ATMEL_LCDC(PC, CC) | ATMEL_LCDC(PC, DVAL) | \219ATMEL_LCDC(PC, MODE) | ATMEL_LCDC(PC, PWR))220221#define ATMEL_LCDC_ALT_CONTROL ( \222ATMEL_LCDC(PE, CC) | ATMEL_LCDC(PE, DVAL) | \223ATMEL_LCDC(PE, MODE) | ATMEL_LCDC(PC, PWR))224225#define ATMEL_LCDC_CONTROL ( \226ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) | \227ATMEL_LCDC(PC, PCLK))228229#define ATMEL_LCDC_PRI_24BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_24B_DATA)230231#define ATMEL_LCDC_ALT_24BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_24B_DATA)232233#define ATMEL_LCDC_PRI_18BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_18B_DATA)234235#define ATMEL_LCDC_ALT_18BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_18B_DATA)236237#define ATMEL_LCDC_PRI_15BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_15B_DATA)238239#define ATMEL_LCDC_ALT_15BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)240241/* Bitmask for all EBI data (D16..D31) pins on port E */242#define ATMEL_EBI_PE_DATA_ALL (0x0000FFFF)243244#endif /* __ASM_ARCH_AT32AP700X_H__ */245246247