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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/blackfin/include/asm/bfin_dma.h
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/*

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 * bfin_dma.h - Blackfin DMA defines/structures/etc...

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 *

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 * Copyright 2004-2010 Analog Devices Inc.

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 *

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 * Licensed under the GPL-2 or later.

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 */

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#ifndef __ASM_BFIN_DMA_H__

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#define __ASM_BFIN_DMA_H__

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#include <linux/types.h>

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/* DMA_CONFIG Masks */

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#define DMAEN			0x0001	/* DMA Channel Enable */

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#define WNR				0x0002	/* Channel Direction (W/R*) */

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#define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */

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#define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */

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#define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */

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#define DMA2D			0x0010	/* DMA Mode (2D/1D*) */

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#define RESTART			0x0020	/* DMA Buffer Clear */

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#define DI_SEL			0x0040	/* Data Interrupt Timing Select */

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#define DI_EN			0x0080	/* Data Interrupt Enable */

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#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer) */

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#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */

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#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */

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#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3 */

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#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4 */

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#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5 */

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#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6 */

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#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7 */

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#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */

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#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */

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#define NDSIZE			0x0f00	/* Next Descriptor Size */

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#define DMAFLOW			0x7000	/* Flow Control */

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#define DMAFLOW_STOP	0x0000	/* Stop Mode */

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#define DMAFLOW_AUTO	0x1000	/* Autobuffer Mode */

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#define DMAFLOW_ARRAY	0x4000	/* Descriptor Array Mode */

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#define DMAFLOW_SMALL	0x6000	/* Small Model Descriptor List Mode */

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#define DMAFLOW_LARGE	0x7000	/* Large Model Descriptor List Mode */

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/* DMA_IRQ_STATUS Masks */

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#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */

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#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */

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#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */

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#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */

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/*

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 * All Blackfin system MMRs are padded to 32bits even if the register

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 * itself is only 16bits.  So use a helper macro to streamline this.

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 */

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#define __BFP(m) u16 m; u16 __pad_##m

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/*

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 * bfin dma registers layout

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 */

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struct bfin_dma_regs {

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	u32 next_desc_ptr;

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	u32 start_addr;

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	__BFP(config);

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	u32 __pad0;

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	__BFP(x_count);

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	__BFP(x_modify);

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	__BFP(y_count);

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	__BFP(y_modify);

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	u32 curr_desc_ptr;

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	u32 curr_addr;

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	__BFP(irq_status);

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	__BFP(peripheral_map);

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	__BFP(curr_x_count);

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	u32 __pad1;

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	__BFP(curr_y_count);

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	u32 __pad2;

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};

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/*

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 * bfin handshake mdma registers layout

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 */

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struct bfin_hmdma_regs {

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	__BFP(control);

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	__BFP(ecinit);

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	__BFP(bcinit);

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	__BFP(ecurgent);

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	__BFP(ecoverflow);

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	__BFP(ecount);

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	__BFP(bcount);

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};

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#undef __BFP

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#endif

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