Path: blob/master/arch/blackfin/include/asm/bfin_sdh.h
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/*1* Blackfin Secure Digital Host (SDH) definitions2*3* Copyright 2008-2010 Analog Devices Inc.4*5* Licensed under the GPL-2 or later.6*/78#ifndef __BFIN_SDH_H__9#define __BFIN_SDH_H__1011/* Platform resources */12struct bfin_sd_host {13int dma_chan;14int irq_int0;15int irq_int1;16u16 pin_req[7];17};1819/* SDH_COMMAND bitmasks */20#define CMD_IDX 0x3f /* Command Index */21#define CMD_RSP (1 << 6) /* Response */22#define CMD_L_RSP (1 << 7) /* Long Response */23#define CMD_INT_E (1 << 8) /* Command Interrupt */24#define CMD_PEND_E (1 << 9) /* Command Pending */25#define CMD_E (1 << 10) /* Command Enable */2627/* SDH_PWR_CTL bitmasks */28#define PWR_ON 0x3 /* Power On */29#define SD_CMD_OD (1 << 6) /* Open Drain Output */30#define ROD_CTL (1 << 7) /* Rod Control */3132/* SDH_CLK_CTL bitmasks */33#define CLKDIV 0xff /* MC_CLK Divisor */34#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */35#define PWR_SV_E (1 << 9) /* Power Save Enable */36#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */37#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */3839/* SDH_RESP_CMD bitmasks */40#define RESP_CMD 0x3f /* Response Command */4142/* SDH_DATA_CTL bitmasks */43#define DTX_E (1 << 0) /* Data Transfer Enable */44#define DTX_DIR (1 << 1) /* Data Transfer Direction */45#define DTX_MODE (1 << 2) /* Data Transfer Mode */46#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */47#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */4849/* SDH_STATUS bitmasks */50#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */51#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */52#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */53#define DAT_TIME_OUT (1 << 3) /* Data Time Out */54#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */55#define RX_OVERRUN (1 << 5) /* Receive Overrun */56#define CMD_RESP_END (1 << 6) /* CMD Response End */57#define CMD_SENT (1 << 7) /* CMD Sent */58#define DAT_END (1 << 8) /* Data End */59#define START_BIT_ERR (1 << 9) /* Start Bit Error */60#define DAT_BLK_END (1 << 10) /* Data Block End */61#define CMD_ACT (1 << 11) /* CMD Active */62#define TX_ACT (1 << 12) /* Transmit Active */63#define RX_ACT (1 << 13) /* Receive Active */64#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */65#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */66#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */67#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */68#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */69#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */70#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */71#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */7273/* SDH_STATUS_CLR bitmasks */74#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */75#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */76#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */77#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */78#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */79#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */80#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */81#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */82#define DAT_END_STAT (1 << 8) /* Data End Status */83#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */84#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */8586/* SDH_MASK0 bitmasks */87#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */88#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */89#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */90#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */91#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */92#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */93#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */94#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */95#define DAT_END_MASK (1 << 8) /* Data End Mask */96#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */97#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */98#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */99#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */100#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */101#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */102#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */103#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */104#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */105#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */106#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */107#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */108#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */109110/* SDH_FIFO_CNT bitmasks */111#define FIFO_COUNT 0x7fff /* FIFO Count */112113/* SDH_E_STATUS bitmasks */114#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */115#define SD_CARD_DET (1 << 4) /* SD Card Detect */116117/* SDH_E_MASK bitmasks */118#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */119#define SCD_MSK (1 << 6) /* Mask Card Detect */120121/* SDH_CFG bitmasks */122#define CLKS_EN (1 << 0) /* Clocks Enable */123#define SD4E (1 << 2) /* SDIO 4-Bit Enable */124#define MWE (1 << 3) /* Moving Window Enable */125#define SD_RST (1 << 4) /* SDMMC Reset */126#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */127#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */128#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */129130/* SDH_RD_WAIT_EN bitmasks */131#define RWR (1 << 0) /* Read Wait Request */132133#endif134135136