Path: blob/master/arch/blackfin/mach-bf518/boards/ezbrd.c
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/*1* Copyright 2004-2009 Analog Devices Inc.2* 2005 National ICT Australia (NICTA)3* Aidan Williams <[email protected]>4*5* Licensed under the GPL-2 or later.6*/78#include <linux/device.h>9#include <linux/platform_device.h>10#include <linux/mtd/mtd.h>11#include <linux/mtd/partitions.h>12#include <linux/mtd/physmap.h>13#include <linux/spi/spi.h>14#include <linux/spi/flash.h>1516#include <linux/i2c.h>17#include <linux/irq.h>18#include <linux/interrupt.h>19#include <asm/dma.h>20#include <asm/bfin5xx_spi.h>21#include <asm/reboot.h>22#include <asm/portmux.h>23#include <asm/dpmc.h>24#include <asm/bfin_sdh.h>25#include <linux/spi/ad7877.h>26#include <net/dsa.h>2728/*29* Name the Board for the /proc/cpuinfo30*/31const char bfin_board_name[] = "ADI BF518F-EZBRD";3233/*34* Driver needs to know address, irq and flag pin.35*/3637#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)38static struct mtd_partition ezbrd_partitions[] = {39{40.name = "bootloader(nor)",41.size = 0x40000,42.offset = 0,43}, {44.name = "linux kernel(nor)",45.size = 0x1C0000,46.offset = MTDPART_OFS_APPEND,47}, {48.name = "file system(nor)",49.size = MTDPART_SIZ_FULL,50.offset = MTDPART_OFS_APPEND,51}52};5354static struct physmap_flash_data ezbrd_flash_data = {55.width = 2,56.parts = ezbrd_partitions,57.nr_parts = ARRAY_SIZE(ezbrd_partitions),58};5960static struct resource ezbrd_flash_resource = {61.start = 0x20000000,62#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)63.end = 0x202fffff,64#else65.end = 0x203fffff,66#endif67.flags = IORESOURCE_MEM,68};6970static struct platform_device ezbrd_flash_device = {71.name = "physmap-flash",72.id = 0,73.dev = {74.platform_data = &ezbrd_flash_data,75},76.num_resources = 1,77.resource = &ezbrd_flash_resource,78};79#endif8081#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)82static struct platform_device rtc_device = {83.name = "rtc-bfin",84.id = -1,85};86#endif8788#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)89#include <linux/bfin_mac.h>90static const unsigned short bfin_mac_peripherals[] = {91P_MII0_ETxD0,92P_MII0_ETxD1,93P_MII0_ETxEN,94P_MII0_ERxD0,95P_MII0_ERxD1,96P_MII0_TxCLK,97P_MII0_PHYINT,98P_MII0_CRS,99P_MII0_MDC,100P_MII0_MDIO,1010102};103104static struct bfin_phydev_platform_data bfin_phydev_data[] = {105{106#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)107.addr = 3,108#else109.addr = 1,110#endif111.irq = IRQ_MAC_PHYINT,112},113};114115static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {116.phydev_number = 1,117.phydev_data = bfin_phydev_data,118.phy_mode = PHY_INTERFACE_MODE_MII,119.mac_peripherals = bfin_mac_peripherals,120#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)121.phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */122#endif123};124125static struct platform_device bfin_mii_bus = {126.name = "bfin_mii_bus",127.dev = {128.platform_data = &bfin_mii_bus_data,129}130};131132static struct platform_device bfin_mac_device = {133.name = "bfin_mac",134.dev = {135.platform_data = &bfin_mii_bus,136}137};138139#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)140static struct dsa_chip_data ksz8893m_switch_chip_data = {141.mii_bus = &bfin_mii_bus.dev,142.port_names = {143NULL,144"eth%d",145"eth%d",146"cpu",147},148};149static struct dsa_platform_data ksz8893m_switch_data = {150.nr_chips = 1,151.netdev = &bfin_mac_device.dev,152.chip = &ksz8893m_switch_chip_data,153};154155static struct platform_device ksz8893m_switch_device = {156.name = "dsa",157.id = 0,158.num_resources = 0,159.dev.platform_data = &ksz8893m_switch_data,160};161#endif162#endif163164#if defined(CONFIG_MTD_M25P80) \165|| defined(CONFIG_MTD_M25P80_MODULE)166static struct mtd_partition bfin_spi_flash_partitions[] = {167{168.name = "bootloader(spi)",169.size = 0x00040000,170.offset = 0,171.mask_flags = MTD_CAP_ROM172}, {173.name = "linux kernel(spi)",174.size = MTDPART_SIZ_FULL,175.offset = MTDPART_OFS_APPEND,176}177};178179static struct flash_platform_data bfin_spi_flash_data = {180.name = "m25p80",181.parts = bfin_spi_flash_partitions,182.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),183.type = "m25p16",184};185186/* SPI flash chip (m25p64) */187static struct bfin5xx_spi_chip spi_flash_chip_info = {188.enable_dma = 0, /* use dma transfer with this chip*/189.bits_per_word = 8,190};191#endif192193#if defined(CONFIG_BFIN_SPI_ADC) \194|| defined(CONFIG_BFIN_SPI_ADC_MODULE)195/* SPI ADC chip */196static struct bfin5xx_spi_chip spi_adc_chip_info = {197.enable_dma = 1, /* use dma transfer with this chip*/198.bits_per_word = 16,199};200#endif201202#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)203#if defined(CONFIG_NET_DSA_KSZ8893M) \204|| defined(CONFIG_NET_DSA_KSZ8893M_MODULE)205/* SPI SWITCH CHIP */206static struct bfin5xx_spi_chip spi_switch_info = {207.enable_dma = 0,208.bits_per_word = 8,209};210#endif211#endif212213#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)214static struct bfin5xx_spi_chip mmc_spi_chip_info = {215.enable_dma = 0,216.bits_per_word = 8,217};218#endif219220#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)221static struct bfin5xx_spi_chip spi_ad7877_chip_info = {222.enable_dma = 0,223.bits_per_word = 16,224};225226static const struct ad7877_platform_data bfin_ad7877_ts_info = {227.model = 7877,228.vref_delay_usecs = 50, /* internal, no capacitor */229.x_plate_ohms = 419,230.y_plate_ohms = 486,231.pressure_max = 1000,232.pressure_min = 0,233.stopacq_polarity = 1,234.first_conversion_delay = 3,235.acquisition_time = 1,236.averaging = 1,237.pen_down_acc_interval = 1,238};239#endif240241#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \242&& defined(CONFIG_SND_SOC_WM8731_SPI)243static struct bfin5xx_spi_chip spi_wm8731_chip_info = {244.enable_dma = 0,245.bits_per_word = 16,246};247#endif248249#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)250static struct bfin5xx_spi_chip spidev_chip_info = {251.enable_dma = 0,252.bits_per_word = 8,253};254#endif255256static struct spi_board_info bfin_spi_board_info[] __initdata = {257#if defined(CONFIG_MTD_M25P80) \258|| defined(CONFIG_MTD_M25P80_MODULE)259{260/* the modalias must be the same as spi device driver name */261.modalias = "m25p80", /* Name of spi_driver for this device */262.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */263.bus_num = 0, /* Framework bus number */264.chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */265.platform_data = &bfin_spi_flash_data,266.controller_data = &spi_flash_chip_info,267.mode = SPI_MODE_3,268},269#endif270271#if defined(CONFIG_BFIN_SPI_ADC) \272|| defined(CONFIG_BFIN_SPI_ADC_MODULE)273{274.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */275.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */276.bus_num = 0, /* Framework bus number */277.chip_select = 1, /* Framework chip select. */278.platform_data = NULL, /* No spi_driver specific config */279.controller_data = &spi_adc_chip_info,280},281#endif282283#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)284#if defined(CONFIG_NET_DSA_KSZ8893M) \285|| defined(CONFIG_NET_DSA_KSZ8893M_MODULE)286{287.modalias = "ksz8893m",288.max_speed_hz = 5000000,289.bus_num = 0,290.chip_select = 1,291.platform_data = NULL,292.controller_data = &spi_switch_info,293.mode = SPI_MODE_3,294},295#endif296#endif297298#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)299{300.modalias = "mmc_spi",301.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */302.bus_num = 0,303.chip_select = 5,304.controller_data = &mmc_spi_chip_info,305.mode = SPI_MODE_3,306},307#endif308#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)309{310.modalias = "ad7877",311.platform_data = &bfin_ad7877_ts_info,312.irq = IRQ_PF8,313.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */314.bus_num = 0,315.chip_select = 2,316.controller_data = &spi_ad7877_chip_info,317},318#endif319#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \320&& defined(CONFIG_SND_SOC_WM8731_SPI)321{322.modalias = "wm8731",323.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */324.bus_num = 0,325.chip_select = 5,326.controller_data = &spi_wm8731_chip_info,327.mode = SPI_MODE_0,328},329#endif330#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)331{332.modalias = "spidev",333.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */334.bus_num = 0,335.chip_select = 1,336.controller_data = &spidev_chip_info,337},338#endif339#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)340{341.modalias = "bfin-lq035q1-spi",342.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */343.bus_num = 0,344.chip_select = 1,345.controller_data = &lq035q1_spi_chip_info,346.mode = SPI_CPHA | SPI_CPOL,347},348#endif349};350351/* SPI controller data */352#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)353/* SPI (0) */354static struct bfin5xx_spi_master bfin_spi0_info = {355.num_chipselect = 6,356.enable_dma = 1, /* master has the ability to do dma transfer */357.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},358};359360static struct resource bfin_spi0_resource[] = {361[0] = {362.start = SPI0_REGBASE,363.end = SPI0_REGBASE + 0xFF,364.flags = IORESOURCE_MEM,365},366[1] = {367.start = CH_SPI0,368.end = CH_SPI0,369.flags = IORESOURCE_DMA,370},371[2] = {372.start = IRQ_SPI0,373.end = IRQ_SPI0,374.flags = IORESOURCE_IRQ,375},376};377378static struct platform_device bfin_spi0_device = {379.name = "bfin-spi",380.id = 0, /* Bus number */381.num_resources = ARRAY_SIZE(bfin_spi0_resource),382.resource = bfin_spi0_resource,383.dev = {384.platform_data = &bfin_spi0_info, /* Passed to driver */385},386};387388/* SPI (1) */389static struct bfin5xx_spi_master bfin_spi1_info = {390.num_chipselect = 6,391.enable_dma = 1, /* master has the ability to do dma transfer */392.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},393};394395static struct resource bfin_spi1_resource[] = {396[0] = {397.start = SPI1_REGBASE,398.end = SPI1_REGBASE + 0xFF,399.flags = IORESOURCE_MEM,400},401[1] = {402.start = CH_SPI1,403.end = CH_SPI1,404.flags = IORESOURCE_DMA,405},406[2] = {407.start = IRQ_SPI1,408.end = IRQ_SPI1,409.flags = IORESOURCE_IRQ,410},411};412413static struct platform_device bfin_spi1_device = {414.name = "bfin-spi",415.id = 1, /* Bus number */416.num_resources = ARRAY_SIZE(bfin_spi1_resource),417.resource = bfin_spi1_resource,418.dev = {419.platform_data = &bfin_spi1_info, /* Passed to driver */420},421};422#endif /* spi master and devices */423424#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)425#ifdef CONFIG_SERIAL_BFIN_UART0426static struct resource bfin_uart0_resources[] = {427{428.start = UART0_THR,429.end = UART0_GCTL+2,430.flags = IORESOURCE_MEM,431},432{433.start = IRQ_UART0_RX,434.end = IRQ_UART0_RX+1,435.flags = IORESOURCE_IRQ,436},437{438.start = IRQ_UART0_ERROR,439.end = IRQ_UART0_ERROR,440.flags = IORESOURCE_IRQ,441},442{443.start = CH_UART0_TX,444.end = CH_UART0_TX,445.flags = IORESOURCE_DMA,446},447{448.start = CH_UART0_RX,449.end = CH_UART0_RX,450.flags = IORESOURCE_DMA,451},452};453454static unsigned short bfin_uart0_peripherals[] = {455P_UART0_TX, P_UART0_RX, 0456};457458static struct platform_device bfin_uart0_device = {459.name = "bfin-uart",460.id = 0,461.num_resources = ARRAY_SIZE(bfin_uart0_resources),462.resource = bfin_uart0_resources,463.dev = {464.platform_data = &bfin_uart0_peripherals, /* Passed to driver */465},466};467#endif468#ifdef CONFIG_SERIAL_BFIN_UART1469static struct resource bfin_uart1_resources[] = {470{471.start = UART1_THR,472.end = UART1_GCTL+2,473.flags = IORESOURCE_MEM,474},475{476.start = IRQ_UART1_RX,477.end = IRQ_UART1_RX+1,478.flags = IORESOURCE_IRQ,479},480{481.start = IRQ_UART1_ERROR,482.end = IRQ_UART1_ERROR,483.flags = IORESOURCE_IRQ,484},485{486.start = CH_UART1_TX,487.end = CH_UART1_TX,488.flags = IORESOURCE_DMA,489},490{491.start = CH_UART1_RX,492.end = CH_UART1_RX,493.flags = IORESOURCE_DMA,494},495};496497static unsigned short bfin_uart1_peripherals[] = {498P_UART1_TX, P_UART1_RX, 0499};500501static struct platform_device bfin_uart1_device = {502.name = "bfin-uart",503.id = 1,504.num_resources = ARRAY_SIZE(bfin_uart1_resources),505.resource = bfin_uart1_resources,506.dev = {507.platform_data = &bfin_uart1_peripherals, /* Passed to driver */508},509};510#endif511#endif512513#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)514#ifdef CONFIG_BFIN_SIR0515static struct resource bfin_sir0_resources[] = {516{517.start = 0xFFC00400,518.end = 0xFFC004FF,519.flags = IORESOURCE_MEM,520},521{522.start = IRQ_UART0_RX,523.end = IRQ_UART0_RX+1,524.flags = IORESOURCE_IRQ,525},526{527.start = CH_UART0_RX,528.end = CH_UART0_RX+1,529.flags = IORESOURCE_DMA,530},531};532533static struct platform_device bfin_sir0_device = {534.name = "bfin_sir",535.id = 0,536.num_resources = ARRAY_SIZE(bfin_sir0_resources),537.resource = bfin_sir0_resources,538};539#endif540#ifdef CONFIG_BFIN_SIR1541static struct resource bfin_sir1_resources[] = {542{543.start = 0xFFC02000,544.end = 0xFFC020FF,545.flags = IORESOURCE_MEM,546},547{548.start = IRQ_UART1_RX,549.end = IRQ_UART1_RX+1,550.flags = IORESOURCE_IRQ,551},552{553.start = CH_UART1_RX,554.end = CH_UART1_RX+1,555.flags = IORESOURCE_DMA,556},557};558559static struct platform_device bfin_sir1_device = {560.name = "bfin_sir",561.id = 1,562.num_resources = ARRAY_SIZE(bfin_sir1_resources),563.resource = bfin_sir1_resources,564};565#endif566#endif567568#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)569static struct platform_device bfin_i2s = {570.name = "bfin-i2s",571.id = CONFIG_SND_BF5XX_SPORT_NUM,572/* TODO: add platform data here */573};574#endif575576#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)577static struct resource bfin_twi0_resource[] = {578[0] = {579.start = TWI0_REGBASE,580.end = TWI0_REGBASE,581.flags = IORESOURCE_MEM,582},583[1] = {584.start = IRQ_TWI,585.end = IRQ_TWI,586.flags = IORESOURCE_IRQ,587},588};589590static struct platform_device i2c_bfin_twi_device = {591.name = "i2c-bfin-twi",592.id = 0,593.num_resources = ARRAY_SIZE(bfin_twi0_resource),594.resource = bfin_twi0_resource,595};596#endif597598static struct i2c_board_info __initdata bfin_i2c_board_info[] = {599#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)600{601I2C_BOARD_INFO("pcf8574_lcd", 0x22),602},603#endif604#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)605{606I2C_BOARD_INFO("pcf8574_keypad", 0x27),607.irq = IRQ_PF8,608},609#endif610#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)611{612I2C_BOARD_INFO("ssm2602", 0x1b),613},614#endif615};616617#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)618#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART619static struct resource bfin_sport0_uart_resources[] = {620{621.start = SPORT0_TCR1,622.end = SPORT0_MRCS3+4,623.flags = IORESOURCE_MEM,624},625{626.start = IRQ_SPORT0_RX,627.end = IRQ_SPORT0_RX+1,628.flags = IORESOURCE_IRQ,629},630{631.start = IRQ_SPORT0_ERROR,632.end = IRQ_SPORT0_ERROR,633.flags = IORESOURCE_IRQ,634},635};636637static unsigned short bfin_sport0_peripherals[] = {638P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,639P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0640};641642static struct platform_device bfin_sport0_uart_device = {643.name = "bfin-sport-uart",644.id = 0,645.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),646.resource = bfin_sport0_uart_resources,647.dev = {648.platform_data = &bfin_sport0_peripherals, /* Passed to driver */649},650};651#endif652#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART653static struct resource bfin_sport1_uart_resources[] = {654{655.start = SPORT1_TCR1,656.end = SPORT1_MRCS3+4,657.flags = IORESOURCE_MEM,658},659{660.start = IRQ_SPORT1_RX,661.end = IRQ_SPORT1_RX+1,662.flags = IORESOURCE_IRQ,663},664{665.start = IRQ_SPORT1_ERROR,666.end = IRQ_SPORT1_ERROR,667.flags = IORESOURCE_IRQ,668},669};670671static unsigned short bfin_sport1_peripherals[] = {672P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,673P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0674};675676static struct platform_device bfin_sport1_uart_device = {677.name = "bfin-sport-uart",678.id = 1,679.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),680.resource = bfin_sport1_uart_resources,681.dev = {682.platform_data = &bfin_sport1_peripherals, /* Passed to driver */683},684};685#endif686#endif687688#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)689#include <linux/input.h>690#include <linux/gpio_keys.h>691692static struct gpio_keys_button bfin_gpio_keys_table[] = {693{BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},694{BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},695};696697static struct gpio_keys_platform_data bfin_gpio_keys_data = {698.buttons = bfin_gpio_keys_table,699.nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),700};701702static struct platform_device bfin_device_gpiokeys = {703.name = "gpio-keys",704.dev = {705.platform_data = &bfin_gpio_keys_data,706},707};708#endif709710#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)711712static struct bfin_sd_host bfin_sdh_data = {713.dma_chan = CH_RSI,714.irq_int0 = IRQ_RSI_INT0,715.pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},716};717718static struct platform_device bf51x_sdh_device = {719.name = "bfin-sdh",720.id = 0,721.dev = {722.platform_data = &bfin_sdh_data,723},724};725#endif726727static const unsigned int cclk_vlev_datasheet[] =728{729VRPAIR(VLEV_100, 400000000),730VRPAIR(VLEV_105, 426000000),731VRPAIR(VLEV_110, 500000000),732VRPAIR(VLEV_115, 533000000),733VRPAIR(VLEV_120, 600000000),734};735736static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {737.tuple_tab = cclk_vlev_datasheet,738.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),739.vr_settling_time = 25 /* us */,740};741742static struct platform_device bfin_dpmc = {743.name = "bfin dpmc",744.dev = {745.platform_data = &bfin_dmpc_vreg_data,746},747};748749static struct platform_device *stamp_devices[] __initdata = {750751&bfin_dpmc,752753#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)754&rtc_device,755#endif756757#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)758&bfin_mii_bus,759&bfin_mac_device,760#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)761&ksz8893m_switch_device,762#endif763#endif764765#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)766&bfin_spi0_device,767&bfin_spi1_device,768#endif769770#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)771#ifdef CONFIG_SERIAL_BFIN_UART0772&bfin_uart0_device,773#endif774#ifdef CONFIG_SERIAL_BFIN_UART1775&bfin_uart1_device,776#endif777#endif778779#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)780#ifdef CONFIG_BFIN_SIR0781&bfin_sir0_device,782#endif783#ifdef CONFIG_BFIN_SIR1784&bfin_sir1_device,785#endif786#endif787788#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)789&i2c_bfin_twi_device,790#endif791792#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)793&bfin_i2s,794#endif795796#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)797#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART798&bfin_sport0_uart_device,799#endif800#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART801&bfin_sport1_uart_device,802#endif803#endif804805#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)806&bfin_device_gpiokeys,807#endif808809#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)810&bf51x_sdh_device,811#endif812813#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)814&ezbrd_flash_device,815#endif816};817818static int __init ezbrd_init(void)819{820printk(KERN_INFO "%s(): registering device resources\n", __func__);821i2c_register_board_info(0, bfin_i2c_board_info,822ARRAY_SIZE(bfin_i2c_board_info));823platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));824spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));825/* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */826peripheral_request(P_AMS2, "ParaFlash");827#if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)828peripheral_request(P_AMS3, "ParaFlash");829#endif830return 0;831}832833arch_initcall(ezbrd_init);834835static struct platform_device *ezbrd_early_devices[] __initdata = {836#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)837#ifdef CONFIG_SERIAL_BFIN_UART0838&bfin_uart0_device,839#endif840#ifdef CONFIG_SERIAL_BFIN_UART1841&bfin_uart1_device,842#endif843#endif844845#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)846#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART847&bfin_sport0_uart_device,848#endif849#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART850&bfin_sport1_uart_device,851#endif852#endif853};854855void __init native_machine_early_platform_add_devices(void)856{857printk(KERN_INFO "register early platform devices\n");858early_platform_add_devices(ezbrd_early_devices,859ARRAY_SIZE(ezbrd_early_devices));860}861862void native_machine_restart(char *cmd)863{864/* workaround reboot hang when booting from SPI */865if ((bfin_read_SYSCR() & 0x7) == 0x3)866bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);867}868869void bfin_get_ether_addr(char *addr)870{871/* the MAC is stored in OTP memory page 0xDF */872u32 ret;873u64 otp_mac;874u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;875876ret = otp_read(0xDF, 0x00, &otp_mac);877if (!(ret & 0x1)) {878char *otp_mac_p = (char *)&otp_mac;879for (ret = 0; ret < 6; ++ret)880addr[ret] = otp_mac_p[5 - ret];881}882}883EXPORT_SYMBOL(bfin_get_ether_addr);884885886