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awilliam
GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/blackfin/mach-bf518/boards/ezbrd.c
10819 views
1
/*
2
* Copyright 2004-2009 Analog Devices Inc.
3
* 2005 National ICT Australia (NICTA)
4
* Aidan Williams <[email protected]>
5
*
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* Licensed under the GPL-2 or later.
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*/
8
9
#include <linux/device.h>
10
#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/spi/spi.h>
15
#include <linux/spi/flash.h>
16
17
#include <linux/i2c.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/dma.h>
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#include <asm/bfin5xx_spi.h>
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#include <asm/reboot.h>
23
#include <asm/portmux.h>
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#include <asm/dpmc.h>
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#include <asm/bfin_sdh.h>
26
#include <linux/spi/ad7877.h>
27
#include <net/dsa.h>
28
29
/*
30
* Name the Board for the /proc/cpuinfo
31
*/
32
const char bfin_board_name[] = "ADI BF518F-EZBRD";
33
34
/*
35
* Driver needs to know address, irq and flag pin.
36
*/
37
38
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
39
static struct mtd_partition ezbrd_partitions[] = {
40
{
41
.name = "bootloader(nor)",
42
.size = 0x40000,
43
.offset = 0,
44
}, {
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.name = "linux kernel(nor)",
46
.size = 0x1C0000,
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.offset = MTDPART_OFS_APPEND,
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}, {
49
.name = "file system(nor)",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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}
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};
54
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static struct physmap_flash_data ezbrd_flash_data = {
56
.width = 2,
57
.parts = ezbrd_partitions,
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.nr_parts = ARRAY_SIZE(ezbrd_partitions),
59
};
60
61
static struct resource ezbrd_flash_resource = {
62
.start = 0x20000000,
63
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
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.end = 0x202fffff,
65
#else
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.end = 0x203fffff,
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#endif
68
.flags = IORESOURCE_MEM,
69
};
70
71
static struct platform_device ezbrd_flash_device = {
72
.name = "physmap-flash",
73
.id = 0,
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.dev = {
75
.platform_data = &ezbrd_flash_data,
76
},
77
.num_resources = 1,
78
.resource = &ezbrd_flash_resource,
79
};
80
#endif
81
82
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
83
static struct platform_device rtc_device = {
84
.name = "rtc-bfin",
85
.id = -1,
86
};
87
#endif
88
89
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
90
#include <linux/bfin_mac.h>
91
static const unsigned short bfin_mac_peripherals[] = {
92
P_MII0_ETxD0,
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P_MII0_ETxD1,
94
P_MII0_ETxEN,
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P_MII0_ERxD0,
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P_MII0_ERxD1,
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P_MII0_TxCLK,
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P_MII0_PHYINT,
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P_MII0_CRS,
100
P_MII0_MDC,
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P_MII0_MDIO,
102
0
103
};
104
105
static struct bfin_phydev_platform_data bfin_phydev_data[] = {
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{
107
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
108
.addr = 3,
109
#else
110
.addr = 1,
111
#endif
112
.irq = IRQ_MAC_PHYINT,
113
},
114
};
115
116
static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
117
.phydev_number = 1,
118
.phydev_data = bfin_phydev_data,
119
.phy_mode = PHY_INTERFACE_MODE_MII,
120
.mac_peripherals = bfin_mac_peripherals,
121
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
122
.phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
123
#endif
124
};
125
126
static struct platform_device bfin_mii_bus = {
127
.name = "bfin_mii_bus",
128
.dev = {
129
.platform_data = &bfin_mii_bus_data,
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}
131
};
132
133
static struct platform_device bfin_mac_device = {
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.name = "bfin_mac",
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.dev = {
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.platform_data = &bfin_mii_bus,
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}
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};
139
140
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
141
static struct dsa_chip_data ksz8893m_switch_chip_data = {
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.mii_bus = &bfin_mii_bus.dev,
143
.port_names = {
144
NULL,
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"eth%d",
146
"eth%d",
147
"cpu",
148
},
149
};
150
static struct dsa_platform_data ksz8893m_switch_data = {
151
.nr_chips = 1,
152
.netdev = &bfin_mac_device.dev,
153
.chip = &ksz8893m_switch_chip_data,
154
};
155
156
static struct platform_device ksz8893m_switch_device = {
157
.name = "dsa",
158
.id = 0,
159
.num_resources = 0,
160
.dev.platform_data = &ksz8893m_switch_data,
161
};
162
#endif
163
#endif
164
165
#if defined(CONFIG_MTD_M25P80) \
166
|| defined(CONFIG_MTD_M25P80_MODULE)
167
static struct mtd_partition bfin_spi_flash_partitions[] = {
168
{
169
.name = "bootloader(spi)",
170
.size = 0x00040000,
171
.offset = 0,
172
.mask_flags = MTD_CAP_ROM
173
}, {
174
.name = "linux kernel(spi)",
175
.size = MTDPART_SIZ_FULL,
176
.offset = MTDPART_OFS_APPEND,
177
}
178
};
179
180
static struct flash_platform_data bfin_spi_flash_data = {
181
.name = "m25p80",
182
.parts = bfin_spi_flash_partitions,
183
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
184
.type = "m25p16",
185
};
186
187
/* SPI flash chip (m25p64) */
188
static struct bfin5xx_spi_chip spi_flash_chip_info = {
189
.enable_dma = 0, /* use dma transfer with this chip*/
190
.bits_per_word = 8,
191
};
192
#endif
193
194
#if defined(CONFIG_BFIN_SPI_ADC) \
195
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
196
/* SPI ADC chip */
197
static struct bfin5xx_spi_chip spi_adc_chip_info = {
198
.enable_dma = 1, /* use dma transfer with this chip*/
199
.bits_per_word = 16,
200
};
201
#endif
202
203
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
204
#if defined(CONFIG_NET_DSA_KSZ8893M) \
205
|| defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
206
/* SPI SWITCH CHIP */
207
static struct bfin5xx_spi_chip spi_switch_info = {
208
.enable_dma = 0,
209
.bits_per_word = 8,
210
};
211
#endif
212
#endif
213
214
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
215
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
216
.enable_dma = 0,
217
.bits_per_word = 8,
218
};
219
#endif
220
221
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
222
static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
223
.enable_dma = 0,
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.bits_per_word = 16,
225
};
226
227
static const struct ad7877_platform_data bfin_ad7877_ts_info = {
228
.model = 7877,
229
.vref_delay_usecs = 50, /* internal, no capacitor */
230
.x_plate_ohms = 419,
231
.y_plate_ohms = 486,
232
.pressure_max = 1000,
233
.pressure_min = 0,
234
.stopacq_polarity = 1,
235
.first_conversion_delay = 3,
236
.acquisition_time = 1,
237
.averaging = 1,
238
.pen_down_acc_interval = 1,
239
};
240
#endif
241
242
#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
243
&& defined(CONFIG_SND_SOC_WM8731_SPI)
244
static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
245
.enable_dma = 0,
246
.bits_per_word = 16,
247
};
248
#endif
249
250
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
251
static struct bfin5xx_spi_chip spidev_chip_info = {
252
.enable_dma = 0,
253
.bits_per_word = 8,
254
};
255
#endif
256
257
static struct spi_board_info bfin_spi_board_info[] __initdata = {
258
#if defined(CONFIG_MTD_M25P80) \
259
|| defined(CONFIG_MTD_M25P80_MODULE)
260
{
261
/* the modalias must be the same as spi device driver name */
262
.modalias = "m25p80", /* Name of spi_driver for this device */
263
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
264
.bus_num = 0, /* Framework bus number */
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.chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
266
.platform_data = &bfin_spi_flash_data,
267
.controller_data = &spi_flash_chip_info,
268
.mode = SPI_MODE_3,
269
},
270
#endif
271
272
#if defined(CONFIG_BFIN_SPI_ADC) \
273
|| defined(CONFIG_BFIN_SPI_ADC_MODULE)
274
{
275
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
276
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
277
.bus_num = 0, /* Framework bus number */
278
.chip_select = 1, /* Framework chip select. */
279
.platform_data = NULL, /* No spi_driver specific config */
280
.controller_data = &spi_adc_chip_info,
281
},
282
#endif
283
284
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
285
#if defined(CONFIG_NET_DSA_KSZ8893M) \
286
|| defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
287
{
288
.modalias = "ksz8893m",
289
.max_speed_hz = 5000000,
290
.bus_num = 0,
291
.chip_select = 1,
292
.platform_data = NULL,
293
.controller_data = &spi_switch_info,
294
.mode = SPI_MODE_3,
295
},
296
#endif
297
#endif
298
299
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
300
{
301
.modalias = "mmc_spi",
302
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
303
.bus_num = 0,
304
.chip_select = 5,
305
.controller_data = &mmc_spi_chip_info,
306
.mode = SPI_MODE_3,
307
},
308
#endif
309
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
310
{
311
.modalias = "ad7877",
312
.platform_data = &bfin_ad7877_ts_info,
313
.irq = IRQ_PF8,
314
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
315
.bus_num = 0,
316
.chip_select = 2,
317
.controller_data = &spi_ad7877_chip_info,
318
},
319
#endif
320
#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
321
&& defined(CONFIG_SND_SOC_WM8731_SPI)
322
{
323
.modalias = "wm8731",
324
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
325
.bus_num = 0,
326
.chip_select = 5,
327
.controller_data = &spi_wm8731_chip_info,
328
.mode = SPI_MODE_0,
329
},
330
#endif
331
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
332
{
333
.modalias = "spidev",
334
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
335
.bus_num = 0,
336
.chip_select = 1,
337
.controller_data = &spidev_chip_info,
338
},
339
#endif
340
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
341
{
342
.modalias = "bfin-lq035q1-spi",
343
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
344
.bus_num = 0,
345
.chip_select = 1,
346
.controller_data = &lq035q1_spi_chip_info,
347
.mode = SPI_CPHA | SPI_CPOL,
348
},
349
#endif
350
};
351
352
/* SPI controller data */
353
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
354
/* SPI (0) */
355
static struct bfin5xx_spi_master bfin_spi0_info = {
356
.num_chipselect = 6,
357
.enable_dma = 1, /* master has the ability to do dma transfer */
358
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
359
};
360
361
static struct resource bfin_spi0_resource[] = {
362
[0] = {
363
.start = SPI0_REGBASE,
364
.end = SPI0_REGBASE + 0xFF,
365
.flags = IORESOURCE_MEM,
366
},
367
[1] = {
368
.start = CH_SPI0,
369
.end = CH_SPI0,
370
.flags = IORESOURCE_DMA,
371
},
372
[2] = {
373
.start = IRQ_SPI0,
374
.end = IRQ_SPI0,
375
.flags = IORESOURCE_IRQ,
376
},
377
};
378
379
static struct platform_device bfin_spi0_device = {
380
.name = "bfin-spi",
381
.id = 0, /* Bus number */
382
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
383
.resource = bfin_spi0_resource,
384
.dev = {
385
.platform_data = &bfin_spi0_info, /* Passed to driver */
386
},
387
};
388
389
/* SPI (1) */
390
static struct bfin5xx_spi_master bfin_spi1_info = {
391
.num_chipselect = 6,
392
.enable_dma = 1, /* master has the ability to do dma transfer */
393
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
394
};
395
396
static struct resource bfin_spi1_resource[] = {
397
[0] = {
398
.start = SPI1_REGBASE,
399
.end = SPI1_REGBASE + 0xFF,
400
.flags = IORESOURCE_MEM,
401
},
402
[1] = {
403
.start = CH_SPI1,
404
.end = CH_SPI1,
405
.flags = IORESOURCE_DMA,
406
},
407
[2] = {
408
.start = IRQ_SPI1,
409
.end = IRQ_SPI1,
410
.flags = IORESOURCE_IRQ,
411
},
412
};
413
414
static struct platform_device bfin_spi1_device = {
415
.name = "bfin-spi",
416
.id = 1, /* Bus number */
417
.num_resources = ARRAY_SIZE(bfin_spi1_resource),
418
.resource = bfin_spi1_resource,
419
.dev = {
420
.platform_data = &bfin_spi1_info, /* Passed to driver */
421
},
422
};
423
#endif /* spi master and devices */
424
425
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
426
#ifdef CONFIG_SERIAL_BFIN_UART0
427
static struct resource bfin_uart0_resources[] = {
428
{
429
.start = UART0_THR,
430
.end = UART0_GCTL+2,
431
.flags = IORESOURCE_MEM,
432
},
433
{
434
.start = IRQ_UART0_RX,
435
.end = IRQ_UART0_RX+1,
436
.flags = IORESOURCE_IRQ,
437
},
438
{
439
.start = IRQ_UART0_ERROR,
440
.end = IRQ_UART0_ERROR,
441
.flags = IORESOURCE_IRQ,
442
},
443
{
444
.start = CH_UART0_TX,
445
.end = CH_UART0_TX,
446
.flags = IORESOURCE_DMA,
447
},
448
{
449
.start = CH_UART0_RX,
450
.end = CH_UART0_RX,
451
.flags = IORESOURCE_DMA,
452
},
453
};
454
455
static unsigned short bfin_uart0_peripherals[] = {
456
P_UART0_TX, P_UART0_RX, 0
457
};
458
459
static struct platform_device bfin_uart0_device = {
460
.name = "bfin-uart",
461
.id = 0,
462
.num_resources = ARRAY_SIZE(bfin_uart0_resources),
463
.resource = bfin_uart0_resources,
464
.dev = {
465
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
466
},
467
};
468
#endif
469
#ifdef CONFIG_SERIAL_BFIN_UART1
470
static struct resource bfin_uart1_resources[] = {
471
{
472
.start = UART1_THR,
473
.end = UART1_GCTL+2,
474
.flags = IORESOURCE_MEM,
475
},
476
{
477
.start = IRQ_UART1_RX,
478
.end = IRQ_UART1_RX+1,
479
.flags = IORESOURCE_IRQ,
480
},
481
{
482
.start = IRQ_UART1_ERROR,
483
.end = IRQ_UART1_ERROR,
484
.flags = IORESOURCE_IRQ,
485
},
486
{
487
.start = CH_UART1_TX,
488
.end = CH_UART1_TX,
489
.flags = IORESOURCE_DMA,
490
},
491
{
492
.start = CH_UART1_RX,
493
.end = CH_UART1_RX,
494
.flags = IORESOURCE_DMA,
495
},
496
};
497
498
static unsigned short bfin_uart1_peripherals[] = {
499
P_UART1_TX, P_UART1_RX, 0
500
};
501
502
static struct platform_device bfin_uart1_device = {
503
.name = "bfin-uart",
504
.id = 1,
505
.num_resources = ARRAY_SIZE(bfin_uart1_resources),
506
.resource = bfin_uart1_resources,
507
.dev = {
508
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
509
},
510
};
511
#endif
512
#endif
513
514
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
515
#ifdef CONFIG_BFIN_SIR0
516
static struct resource bfin_sir0_resources[] = {
517
{
518
.start = 0xFFC00400,
519
.end = 0xFFC004FF,
520
.flags = IORESOURCE_MEM,
521
},
522
{
523
.start = IRQ_UART0_RX,
524
.end = IRQ_UART0_RX+1,
525
.flags = IORESOURCE_IRQ,
526
},
527
{
528
.start = CH_UART0_RX,
529
.end = CH_UART0_RX+1,
530
.flags = IORESOURCE_DMA,
531
},
532
};
533
534
static struct platform_device bfin_sir0_device = {
535
.name = "bfin_sir",
536
.id = 0,
537
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
538
.resource = bfin_sir0_resources,
539
};
540
#endif
541
#ifdef CONFIG_BFIN_SIR1
542
static struct resource bfin_sir1_resources[] = {
543
{
544
.start = 0xFFC02000,
545
.end = 0xFFC020FF,
546
.flags = IORESOURCE_MEM,
547
},
548
{
549
.start = IRQ_UART1_RX,
550
.end = IRQ_UART1_RX+1,
551
.flags = IORESOURCE_IRQ,
552
},
553
{
554
.start = CH_UART1_RX,
555
.end = CH_UART1_RX+1,
556
.flags = IORESOURCE_DMA,
557
},
558
};
559
560
static struct platform_device bfin_sir1_device = {
561
.name = "bfin_sir",
562
.id = 1,
563
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
564
.resource = bfin_sir1_resources,
565
};
566
#endif
567
#endif
568
569
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
570
static struct platform_device bfin_i2s = {
571
.name = "bfin-i2s",
572
.id = CONFIG_SND_BF5XX_SPORT_NUM,
573
/* TODO: add platform data here */
574
};
575
#endif
576
577
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
578
static struct resource bfin_twi0_resource[] = {
579
[0] = {
580
.start = TWI0_REGBASE,
581
.end = TWI0_REGBASE,
582
.flags = IORESOURCE_MEM,
583
},
584
[1] = {
585
.start = IRQ_TWI,
586
.end = IRQ_TWI,
587
.flags = IORESOURCE_IRQ,
588
},
589
};
590
591
static struct platform_device i2c_bfin_twi_device = {
592
.name = "i2c-bfin-twi",
593
.id = 0,
594
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
595
.resource = bfin_twi0_resource,
596
};
597
#endif
598
599
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
600
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
601
{
602
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
603
},
604
#endif
605
#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
606
{
607
I2C_BOARD_INFO("pcf8574_keypad", 0x27),
608
.irq = IRQ_PF8,
609
},
610
#endif
611
#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
612
{
613
I2C_BOARD_INFO("ssm2602", 0x1b),
614
},
615
#endif
616
};
617
618
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
619
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
620
static struct resource bfin_sport0_uart_resources[] = {
621
{
622
.start = SPORT0_TCR1,
623
.end = SPORT0_MRCS3+4,
624
.flags = IORESOURCE_MEM,
625
},
626
{
627
.start = IRQ_SPORT0_RX,
628
.end = IRQ_SPORT0_RX+1,
629
.flags = IORESOURCE_IRQ,
630
},
631
{
632
.start = IRQ_SPORT0_ERROR,
633
.end = IRQ_SPORT0_ERROR,
634
.flags = IORESOURCE_IRQ,
635
},
636
};
637
638
static unsigned short bfin_sport0_peripherals[] = {
639
P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
640
P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
641
};
642
643
static struct platform_device bfin_sport0_uart_device = {
644
.name = "bfin-sport-uart",
645
.id = 0,
646
.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
647
.resource = bfin_sport0_uart_resources,
648
.dev = {
649
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
650
},
651
};
652
#endif
653
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
654
static struct resource bfin_sport1_uart_resources[] = {
655
{
656
.start = SPORT1_TCR1,
657
.end = SPORT1_MRCS3+4,
658
.flags = IORESOURCE_MEM,
659
},
660
{
661
.start = IRQ_SPORT1_RX,
662
.end = IRQ_SPORT1_RX+1,
663
.flags = IORESOURCE_IRQ,
664
},
665
{
666
.start = IRQ_SPORT1_ERROR,
667
.end = IRQ_SPORT1_ERROR,
668
.flags = IORESOURCE_IRQ,
669
},
670
};
671
672
static unsigned short bfin_sport1_peripherals[] = {
673
P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
674
P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
675
};
676
677
static struct platform_device bfin_sport1_uart_device = {
678
.name = "bfin-sport-uart",
679
.id = 1,
680
.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
681
.resource = bfin_sport1_uart_resources,
682
.dev = {
683
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
684
},
685
};
686
#endif
687
#endif
688
689
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
690
#include <linux/input.h>
691
#include <linux/gpio_keys.h>
692
693
static struct gpio_keys_button bfin_gpio_keys_table[] = {
694
{BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
695
{BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
696
};
697
698
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
699
.buttons = bfin_gpio_keys_table,
700
.nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
701
};
702
703
static struct platform_device bfin_device_gpiokeys = {
704
.name = "gpio-keys",
705
.dev = {
706
.platform_data = &bfin_gpio_keys_data,
707
},
708
};
709
#endif
710
711
#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
712
713
static struct bfin_sd_host bfin_sdh_data = {
714
.dma_chan = CH_RSI,
715
.irq_int0 = IRQ_RSI_INT0,
716
.pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
717
};
718
719
static struct platform_device bf51x_sdh_device = {
720
.name = "bfin-sdh",
721
.id = 0,
722
.dev = {
723
.platform_data = &bfin_sdh_data,
724
},
725
};
726
#endif
727
728
static const unsigned int cclk_vlev_datasheet[] =
729
{
730
VRPAIR(VLEV_100, 400000000),
731
VRPAIR(VLEV_105, 426000000),
732
VRPAIR(VLEV_110, 500000000),
733
VRPAIR(VLEV_115, 533000000),
734
VRPAIR(VLEV_120, 600000000),
735
};
736
737
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
738
.tuple_tab = cclk_vlev_datasheet,
739
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
740
.vr_settling_time = 25 /* us */,
741
};
742
743
static struct platform_device bfin_dpmc = {
744
.name = "bfin dpmc",
745
.dev = {
746
.platform_data = &bfin_dmpc_vreg_data,
747
},
748
};
749
750
static struct platform_device *stamp_devices[] __initdata = {
751
752
&bfin_dpmc,
753
754
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
755
&rtc_device,
756
#endif
757
758
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
759
&bfin_mii_bus,
760
&bfin_mac_device,
761
#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
762
&ksz8893m_switch_device,
763
#endif
764
#endif
765
766
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
767
&bfin_spi0_device,
768
&bfin_spi1_device,
769
#endif
770
771
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
772
#ifdef CONFIG_SERIAL_BFIN_UART0
773
&bfin_uart0_device,
774
#endif
775
#ifdef CONFIG_SERIAL_BFIN_UART1
776
&bfin_uart1_device,
777
#endif
778
#endif
779
780
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
781
#ifdef CONFIG_BFIN_SIR0
782
&bfin_sir0_device,
783
#endif
784
#ifdef CONFIG_BFIN_SIR1
785
&bfin_sir1_device,
786
#endif
787
#endif
788
789
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
790
&i2c_bfin_twi_device,
791
#endif
792
793
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
794
&bfin_i2s,
795
#endif
796
797
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
798
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
799
&bfin_sport0_uart_device,
800
#endif
801
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
802
&bfin_sport1_uart_device,
803
#endif
804
#endif
805
806
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
807
&bfin_device_gpiokeys,
808
#endif
809
810
#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
811
&bf51x_sdh_device,
812
#endif
813
814
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
815
&ezbrd_flash_device,
816
#endif
817
};
818
819
static int __init ezbrd_init(void)
820
{
821
printk(KERN_INFO "%s(): registering device resources\n", __func__);
822
i2c_register_board_info(0, bfin_i2c_board_info,
823
ARRAY_SIZE(bfin_i2c_board_info));
824
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
825
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
826
/* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
827
peripheral_request(P_AMS2, "ParaFlash");
828
#if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
829
peripheral_request(P_AMS3, "ParaFlash");
830
#endif
831
return 0;
832
}
833
834
arch_initcall(ezbrd_init);
835
836
static struct platform_device *ezbrd_early_devices[] __initdata = {
837
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
838
#ifdef CONFIG_SERIAL_BFIN_UART0
839
&bfin_uart0_device,
840
#endif
841
#ifdef CONFIG_SERIAL_BFIN_UART1
842
&bfin_uart1_device,
843
#endif
844
#endif
845
846
#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
847
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
848
&bfin_sport0_uart_device,
849
#endif
850
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
851
&bfin_sport1_uart_device,
852
#endif
853
#endif
854
};
855
856
void __init native_machine_early_platform_add_devices(void)
857
{
858
printk(KERN_INFO "register early platform devices\n");
859
early_platform_add_devices(ezbrd_early_devices,
860
ARRAY_SIZE(ezbrd_early_devices));
861
}
862
863
void native_machine_restart(char *cmd)
864
{
865
/* workaround reboot hang when booting from SPI */
866
if ((bfin_read_SYSCR() & 0x7) == 0x3)
867
bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
868
}
869
870
void bfin_get_ether_addr(char *addr)
871
{
872
/* the MAC is stored in OTP memory page 0xDF */
873
u32 ret;
874
u64 otp_mac;
875
u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
876
877
ret = otp_read(0xDF, 0x00, &otp_mac);
878
if (!(ret & 0x1)) {
879
char *otp_mac_p = (char *)&otp_mac;
880
for (ret = 0; ret < 6; ++ret)
881
addr[ret] = otp_mac_p[5 - ret];
882
}
883
}
884
EXPORT_SYMBOL(bfin_get_ether_addr);
885
886