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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/blackfin/mach-bf537/include/mach/mem_map.h
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/*

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 * BF537 memory map

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 *

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 * Copyright 2004-2009 Analog Devices Inc.

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 * Licensed under the GPL-2 or later.

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 */

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#ifndef __BFIN_MACH_MEM_MAP_H__

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#define __BFIN_MACH_MEM_MAP_H__

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#ifndef __BFIN_MEM_MAP_H__

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# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"

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#endif

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/* Async Memory Banks */

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#define ASYNC_BANK3_BASE	0x20300000	 /* Async Bank 3 */

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#define ASYNC_BANK3_SIZE	0x00100000	/* 1M */

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#define ASYNC_BANK2_BASE	0x20200000	 /* Async Bank 2 */

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#define ASYNC_BANK2_SIZE	0x00100000	/* 1M */

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#define ASYNC_BANK1_BASE	0x20100000	 /* Async Bank 1 */

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#define ASYNC_BANK1_SIZE	0x00100000	/* 1M */

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#define ASYNC_BANK0_BASE	0x20000000	 /* Async Bank 0 */

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#define ASYNC_BANK0_SIZE	0x00100000	/* 1M */

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/* Boot ROM Memory */

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#define BOOT_ROM_START		0xEF000000

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#define BOOT_ROM_LENGTH		0x800

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/* Level 1 Memory */

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/* Memory Map for ADSP-BF537 processors */

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#ifdef CONFIG_BFIN_ICACHE

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#define BFIN_ICACHESIZE	(16*1024)

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#else

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#define BFIN_ICACHESIZE	(0*1024)

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#endif

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#ifdef CONFIG_BF537

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#define L1_CODE_START       0xFFA00000

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#define L1_DATA_A_START     0xFF800000

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#define L1_DATA_B_START     0xFF900000

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#define L1_CODE_LENGTH      0xC000

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#ifdef CONFIG_BFIN_DCACHE

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#ifdef CONFIG_BFIN_DCACHE_BANKA

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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)

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#define L1_DATA_B_LENGTH      0x8000

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#define BFIN_DCACHESIZE	(16*1024)

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#define BFIN_DSUPBANKS	1

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#else

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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)

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#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)

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#define BFIN_DCACHESIZE	(32*1024)

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#define BFIN_DSUPBANKS	2

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#endif

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#else

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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      0x8000

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#define L1_DATA_B_LENGTH      0x8000

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#define BFIN_DCACHESIZE	(0*1024)

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#define BFIN_DSUPBANKS	0

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#endif /*CONFIG_BFIN_DCACHE*/

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#endif /*CONFIG_BF537*/

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/* Memory Map for ADSP-BF536 processors */

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#ifdef CONFIG_BF536

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#define L1_CODE_START       0xFFA00000

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#define L1_DATA_A_START     0xFF804000

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#define L1_DATA_B_START     0xFF904000

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#define L1_CODE_LENGTH      0xC000

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#ifdef CONFIG_BFIN_DCACHE

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#ifdef CONFIG_BFIN_DCACHE_BANKA

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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)

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#define L1_DATA_B_LENGTH      0x4000

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#define BFIN_DCACHESIZE	(16*1024)

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#define BFIN_DSUPBANKS	1

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#else

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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)

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#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)

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#define BFIN_DCACHESIZE	(32*1024)

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#define BFIN_DSUPBANKS	2

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#endif

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#else

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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      0x4000

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#define L1_DATA_B_LENGTH      0x4000

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#define BFIN_DCACHESIZE	(0*1024)

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#define BFIN_DSUPBANKS	0

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#endif /*CONFIG_BFIN_DCACHE*/

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#endif

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/* Memory Map for ADSP-BF534 processors */

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#ifdef CONFIG_BF534

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#define L1_CODE_START       0xFFA00000

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#define L1_DATA_A_START     0xFF800000

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#define L1_DATA_B_START     0xFF900000

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#define L1_CODE_LENGTH      0xC000

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#ifdef CONFIG_BFIN_DCACHE

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#ifdef CONFIG_BFIN_DCACHE_BANKA

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#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)

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#define L1_DATA_B_LENGTH      0x8000

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#define BFIN_DCACHESIZE	(16*1024)

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#define BFIN_DSUPBANKS	1

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#else

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#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)

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#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)

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#define BFIN_DCACHESIZE	(32*1024)

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#define BFIN_DSUPBANKS	2

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#endif

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#else

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#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)

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#define L1_DATA_A_LENGTH      0x8000

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#define L1_DATA_B_LENGTH      0x8000

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#define BFIN_DCACHESIZE	(0*1024)

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#define BFIN_DSUPBANKS	0

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#endif /*CONFIG_BFIN_DCACHE*/

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#endif

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#endif

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