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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/blackfin/mach-bf538/dma.c
10817 views
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/*

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 * the simple DMA Implementation for Blackfin

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 *

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 * Copyright 2008 Analog Devices Inc.

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 *

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 * Licensed under the GPL-2 or later.

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 */

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#include <linux/module.h>

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#include <asm/blackfin.h>

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#include <asm/dma.h>

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struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {

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	(struct dma_register *) DMA0_NEXT_DESC_PTR,

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	(struct dma_register *) DMA1_NEXT_DESC_PTR,

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	(struct dma_register *) DMA2_NEXT_DESC_PTR,

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	(struct dma_register *) DMA3_NEXT_DESC_PTR,

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	(struct dma_register *) DMA4_NEXT_DESC_PTR,

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	(struct dma_register *) DMA5_NEXT_DESC_PTR,

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	(struct dma_register *) DMA6_NEXT_DESC_PTR,

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	(struct dma_register *) DMA7_NEXT_DESC_PTR,

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	(struct dma_register *) DMA8_NEXT_DESC_PTR,

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	(struct dma_register *) DMA9_NEXT_DESC_PTR,

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	(struct dma_register *) DMA10_NEXT_DESC_PTR,

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	(struct dma_register *) DMA11_NEXT_DESC_PTR,

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	(struct dma_register *) DMA12_NEXT_DESC_PTR,

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	(struct dma_register *) DMA13_NEXT_DESC_PTR,

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	(struct dma_register *) DMA14_NEXT_DESC_PTR,

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	(struct dma_register *) DMA15_NEXT_DESC_PTR,

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	(struct dma_register *) DMA16_NEXT_DESC_PTR,

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	(struct dma_register *) DMA17_NEXT_DESC_PTR,

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	(struct dma_register *) DMA18_NEXT_DESC_PTR,

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	(struct dma_register *) DMA19_NEXT_DESC_PTR,

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	(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,

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	(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,

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	(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,

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	(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,

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	(struct dma_register *) MDMA_D2_NEXT_DESC_PTR,

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	(struct dma_register *) MDMA_S2_NEXT_DESC_PTR,

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	(struct dma_register *) MDMA_D3_NEXT_DESC_PTR,

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	(struct dma_register *) MDMA_S3_NEXT_DESC_PTR,

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};

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EXPORT_SYMBOL(dma_io_base_addr);

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int channel2irq(unsigned int channel)

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{

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	int ret_irq = -1;

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	switch (channel) {

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	case CH_PPI:

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		ret_irq = IRQ_PPI;

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		break;

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	case CH_UART0_RX:

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		ret_irq = IRQ_UART0_RX;

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		break;

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	case CH_UART0_TX:

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		ret_irq = IRQ_UART0_TX;

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		break;

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	case CH_UART1_RX:

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		ret_irq = IRQ_UART1_RX;

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		break;

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	case CH_UART1_TX:

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		ret_irq = IRQ_UART1_TX;

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		break;

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	case CH_UART2_RX:

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		ret_irq = IRQ_UART2_RX;

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		break;

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	case CH_UART2_TX:

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		ret_irq = IRQ_UART2_TX;

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		break;

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	case CH_SPORT0_RX:

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		ret_irq = IRQ_SPORT0_RX;

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		break;

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	case CH_SPORT0_TX:

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		ret_irq = IRQ_SPORT0_TX;

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		break;

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	case CH_SPORT1_RX:

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		ret_irq = IRQ_SPORT1_RX;

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		break;

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	case CH_SPORT1_TX:

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		ret_irq = IRQ_SPORT1_TX;

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		break;

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	case CH_SPORT2_RX:

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		ret_irq = IRQ_SPORT2_RX;

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		break;

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	case CH_SPORT2_TX:

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		ret_irq = IRQ_SPORT2_TX;

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		break;

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	case CH_SPORT3_RX:

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		ret_irq = IRQ_SPORT3_RX;

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		break;

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	case CH_SPORT3_TX:

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		ret_irq = IRQ_SPORT3_TX;

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		break;

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	case CH_SPI0:

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		ret_irq = IRQ_SPI0;

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		break;

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	case CH_SPI1:

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		ret_irq = IRQ_SPI1;

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		break;

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	case CH_SPI2:

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		ret_irq = IRQ_SPI2;

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		break;

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	case CH_MEM_STREAM0_SRC:

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	case CH_MEM_STREAM0_DEST:

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		ret_irq = IRQ_MEM0_DMA0;

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		break;

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	case CH_MEM_STREAM1_SRC:

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	case CH_MEM_STREAM1_DEST:

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		ret_irq = IRQ_MEM0_DMA1;

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		break;

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	case CH_MEM_STREAM2_SRC:

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	case CH_MEM_STREAM2_DEST:

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		ret_irq = IRQ_MEM1_DMA0;

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		break;

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	case CH_MEM_STREAM3_SRC:

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	case CH_MEM_STREAM3_DEST:

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		ret_irq = IRQ_MEM1_DMA1;

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		break;

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	}

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	return ret_irq;

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}

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