Path: blob/master/arch/blackfin/mach-bf548/include/mach/defBF542.h
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/*1* Copyright 2007-2010 Analog Devices Inc.2*3* Licensed under the ADI BSD license or the GPL-2 (or later)4*/56#ifndef _DEF_BF542_H7#define _DEF_BF542_H89/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */10#include "defBF54x_base.h"1112/* The following are the #defines needed by ADSP-BF542 that are not in the common header */1314/* ATAPI Registers */1516#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */17#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */18#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */19#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */20#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */21#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */22#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */23#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */24#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */25#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */26#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */27#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */28#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */29#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */30#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */31#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */32#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */33#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */34#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */35#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */36#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */37#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */38#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */39#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */40#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */4142/* SDH Registers */4344#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */45#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */46#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */47#define SDH_COMMAND 0xffc0390c /* SDH Command */48#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */49#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */50#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */51#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */52#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */53#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */54#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */55#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */56#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */57#define SDH_STATUS 0xffc03934 /* SDH Status */58#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */59#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */60#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */61#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */62#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */63#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */64#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */65#define SDH_CFG 0xffc039c8 /* SDH Configuration */66#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */67#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */68#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */69#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */70#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */71#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */72#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */73#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */74#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */7576/* USB Control Registers */7778#define USB_FADDR 0xffc03c00 /* Function address register */79#define USB_POWER 0xffc03c04 /* Power management register */80#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */81#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */82#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */83#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */84#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */85#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */86#define USB_FRAME 0xffc03c20 /* USB frame number */87#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */88#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */89#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */90#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */9192/* USB Packet Control Registers */9394#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */95#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */96#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */97#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */98#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */99#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */100#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */101#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */102#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */103#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */104#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */105#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */106#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */107108/* USB Endpoint FIFO Registers */109110#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */111#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */112#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */113#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */114#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */115#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */116#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */117#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */118119/* USB OTG Control Registers */120121#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */122#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */123#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */124125/* USB Phy Control Registers */126127#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */128#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */129#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */130#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */131#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */132133/* (APHY_CNTRL is for ADI usage only) */134135#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */136137/* (APHY_CALIB is for ADI usage only) */138139#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */140#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */141142/* (PHY_TEST is for ADI usage only) */143144#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */145#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */146#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */147148/* USB Endpoint 0 Control Registers */149150#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */151#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */152#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */153#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */154#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */155#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */156#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */157#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */158#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */159160/* USB Endpoint 1 Control Registers */161162#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */163#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */164#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */165#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */166#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */167#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */168#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */169#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */170#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */171#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */172173/* USB Endpoint 2 Control Registers */174175#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */176#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */177#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */178#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */179#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */180#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */181#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */182#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */183#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */184#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */185186/* USB Endpoint 3 Control Registers */187188#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */189#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */190#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */191#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */192#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */193#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */194#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */195#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */196#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */197#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */198199/* USB Endpoint 4 Control Registers */200201#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */202#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */203#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */204#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */205#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */206#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */207#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */208#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */209#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */210#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */211212/* USB Endpoint 5 Control Registers */213214#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */215#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */216#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */217#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */218#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */219#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */220#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */221#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */222#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */223#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */224225/* USB Endpoint 6 Control Registers */226227#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */228#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */229#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */230#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */231#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */232#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */233#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */234#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */235#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */236#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */237238/* USB Endpoint 7 Control Registers */239240#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */241#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */242#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */243#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */244#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */245#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */246#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */247#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */248#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */249#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */250#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */251#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */252253/* USB Channel 0 Config Registers */254255#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */256#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */257#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */258#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */259#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */260261/* USB Channel 1 Config Registers */262263#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */264#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */265#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */266#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */267#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */268269/* USB Channel 2 Config Registers */270271#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */272#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */273#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */274#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */275#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */276277/* USB Channel 3 Config Registers */278279#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */280#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */281#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */282#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */283#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */284285/* USB Channel 4 Config Registers */286287#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */288#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */289#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */290#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */291#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */292293/* USB Channel 5 Config Registers */294295#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */296#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */297#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */298#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */299#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */300301/* USB Channel 6 Config Registers */302303#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */304#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */305#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */306#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */307#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */308309/* USB Channel 7 Config Registers */310311#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */312#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */313#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */314#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */315#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */316317/* Keypad Registers */318319#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */320#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */321#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */322#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */323#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */324#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */325326327/* ********************************************************** */328/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */329/* and MULTI BIT READ MACROS */330/* ********************************************************** */331332/* Bit masks for KPAD_CTL */333334#define KPAD_EN 0x1 /* Keypad Enable */335#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */336#define KPAD_ROWEN 0x1c00 /* Row Enable Width */337#define KPAD_COLEN 0xe000 /* Column Enable Width */338339/* Bit masks for KPAD_PRESCALE */340341#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */342343/* Bit masks for KPAD_MSEL */344345#define DBON_SCALE 0xff /* Debounce Scale Value */346#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */347348/* Bit masks for KPAD_ROWCOL */349350#define KPAD_ROW 0xff /* Rows Pressed */351#define KPAD_COL 0xff00 /* Columns Pressed */352353/* Bit masks for KPAD_STAT */354355#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */356#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */357#define KPAD_PRESSED 0x8 /* Key press current status */358359/* Bit masks for KPAD_SOFTEVAL */360361#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */362363/* Bit masks for ATAPI_CONTROL */364365#define PIO_START 0x1 /* Start PIO/Reg Op */366#define MULTI_START 0x2 /* Start Multi-DMA Op */367#define ULTRA_START 0x4 /* Start Ultra-DMA Op */368#define XFER_DIR 0x8 /* Transfer Direction */369#define IORDY_EN 0x10 /* IORDY Enable */370#define FIFO_FLUSH 0x20 /* Flush FIFOs */371#define SOFT_RST 0x40 /* Soft Reset */372#define DEV_RST 0x80 /* Device Reset */373#define TFRCNT_RST 0x100 /* Trans Count Reset */374#define END_ON_TERM 0x200 /* End/Terminate Select */375#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */376#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */377378/* Bit masks for ATAPI_STATUS */379380#define PIO_XFER_ON 0x1 /* PIO transfer in progress */381#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */382#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */383#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */384385/* Bit masks for ATAPI_DEV_ADDR */386387#define DEV_ADDR 0x1f /* Device Address */388389/* Bit masks for ATAPI_INT_MASK */390391#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */392#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */393#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */394#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */395#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */396#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */397#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */398#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */399#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */400401/* Bit masks for ATAPI_INT_STATUS */402403#define ATAPI_DEV_INT 0x1 /* Device interrupt status */404#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */405#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */406#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */407#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */408#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */409#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */410#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */411#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */412413/* Bit masks for ATAPI_LINE_STATUS */414415#define ATAPI_INTR 0x1 /* Device interrupt to host line status */416#define ATAPI_DASP 0x2 /* Device dasp to host line status */417#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */418#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */419#define ATAPI_ADDR 0x70 /* ATAPI address line status */420#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */421#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */422#define ATAPI_DIOWN 0x200 /* ATAPI write line status */423#define ATAPI_DIORN 0x400 /* ATAPI read line status */424#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */425426/* Bit masks for ATAPI_SM_STATE */427428#define PIO_CSTATE 0xf /* PIO mode state machine current state */429#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */430#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */431#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */432433/* Bit masks for ATAPI_TERMINATE */434435#define ATAPI_HOST_TERM 0x1 /* Host terminationation */436437/* Bit masks for ATAPI_REG_TIM_0 */438439#define T2_REG 0xff /* End of cycle time for register access transfers */440#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */441442/* Bit masks for ATAPI_PIO_TIM_0 */443444#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */445#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */446#define T4_REG 0xf000 /* DIOW data hold */447448/* Bit masks for ATAPI_PIO_TIM_1 */449450#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */451452/* Bit masks for ATAPI_MULTI_TIM_0 */453454#define TD 0xff /* DIOR/DIOW asserted pulsewidth */455#define TM 0xff00 /* Time from address valid to DIOR/DIOW */456457/* Bit masks for ATAPI_MULTI_TIM_1 */458459#define TKW 0xff /* Selects DIOW negated pulsewidth */460#define TKR 0xff00 /* Selects DIOR negated pulsewidth */461462/* Bit masks for ATAPI_MULTI_TIM_2 */463464#define TH 0xff /* Selects DIOW data hold */465#define TEOC 0xff00 /* Selects end of cycle for DMA */466467/* Bit masks for ATAPI_ULTRA_TIM_0 */468469#define TACK 0xff /* Selects setup and hold times for TACK */470#define TENV 0xff00 /* Selects envelope time */471472/* Bit masks for ATAPI_ULTRA_TIM_1 */473474#define TDVS 0xff /* Selects data valid setup time */475#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */476477/* Bit masks for ATAPI_ULTRA_TIM_2 */478479#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */480#define TMLI 0xff00 /* Selects interlock time */481482/* Bit masks for ATAPI_ULTRA_TIM_3 */483484#define TZAH 0xff /* Selects minimum delay required for output */485#define READY_PAUSE 0xff00 /* Selects ready to pause */486487/* Bit masks for USB_FADDR */488489#define FUNCTION_ADDRESS 0x7f /* Function address */490491/* Bit masks for USB_POWER */492493#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */494#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */495#define RESUME_MODE 0x4 /* DMA Mode */496#define RESET 0x8 /* Reset indicator */497#define HS_MODE 0x10 /* High Speed mode indicator */498#define HS_ENABLE 0x20 /* high Speed Enable */499#define SOFT_CONN 0x40 /* Soft connect */500#define ISO_UPDATE 0x80 /* Isochronous update */501502/* Bit masks for USB_INTRTX */503504#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */505#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */506#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */507#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */508#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */509#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */510#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */511#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */512513/* Bit masks for USB_INTRRX */514515#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */516#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */517#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */518#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */519#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */520#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */521#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */522523/* Bit masks for USB_INTRTXE */524525#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */526#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */527#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */528#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */529#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */530#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */531#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */532#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */533534/* Bit masks for USB_INTRRXE */535536#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */537#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */538#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */539#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */540#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */541#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */542#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */543544/* Bit masks for USB_INTRUSB */545546#define SUSPEND_B 0x1 /* Suspend indicator */547#define RESUME_B 0x2 /* Resume indicator */548#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */549#define SOF_B 0x8 /* Start of frame */550#define CONN_B 0x10 /* Connection indicator */551#define DISCON_B 0x20 /* Disconnect indicator */552#define SESSION_REQ_B 0x40 /* Session Request */553#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */554555/* Bit masks for USB_INTRUSBE */556557#define SUSPEND_BE 0x1 /* Suspend indicator int enable */558#define RESUME_BE 0x2 /* Resume indicator int enable */559#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */560#define SOF_BE 0x8 /* Start of frame int enable */561#define CONN_BE 0x10 /* Connection indicator int enable */562#define DISCON_BE 0x20 /* Disconnect indicator int enable */563#define SESSION_REQ_BE 0x40 /* Session Request int enable */564#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */565566/* Bit masks for USB_FRAME */567568#define FRAME_NUMBER 0x7ff /* Frame number */569570/* Bit masks for USB_INDEX */571572#define SELECTED_ENDPOINT 0xf /* selected endpoint */573574/* Bit masks for USB_GLOBAL_CTL */575576#define GLOBAL_ENA 0x1 /* enables USB module */577#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */578#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */579#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */580#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */581#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */582#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */583#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */584#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */585#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */586#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */587#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */588#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */589#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */590#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */591592/* Bit masks for USB_OTG_DEV_CTL */593594#define SESSION 0x1 /* session indicator */595#define HOST_REQ 0x2 /* Host negotiation request */596#define HOST_MODE 0x4 /* indicates USBDRC is a host */597#define VBUS0 0x8 /* Vbus level indicator[0] */598#define VBUS1 0x10 /* Vbus level indicator[1] */599#define LSDEV 0x20 /* Low-speed indicator */600#define FSDEV 0x40 /* Full or High-speed indicator */601#define B_DEVICE 0x80 /* A' or 'B' device indicator */602603/* Bit masks for USB_OTG_VBUS_IRQ */604605#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */606#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */607#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */608#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */609#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */610#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */611612/* Bit masks for USB_OTG_VBUS_MASK */613614#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */615#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */616#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */617#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */618#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */619#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */620621/* Bit masks for USB_CSR0 */622623#define RXPKTRDY 0x1 /* data packet receive indicator */624#define TXPKTRDY 0x2 /* data packet in FIFO indicator */625#define STALL_SENT 0x4 /* STALL handshake sent */626#define DATAEND 0x8 /* Data end indicator */627#define SETUPEND 0x10 /* Setup end */628#define SENDSTALL 0x20 /* Send STALL handshake */629#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */630#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */631#define FLUSHFIFO 0x100 /* flush endpoint FIFO */632#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */633#define SETUPPKT_H 0x8 /* send Setup token host mode */634#define ERROR_H 0x10 /* timeout error indicator host mode */635#define REQPKT_H 0x20 /* Request an IN transaction host mode */636#define STATUSPKT_H 0x40 /* Status stage transaction host mode */637#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */638639/* Bit masks for USB_COUNT0 */640641#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */642643/* Bit masks for USB_NAKLIMIT0 */644645#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */646647/* Bit masks for USB_TX_MAX_PACKET */648649#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */650651/* Bit masks for USB_RX_MAX_PACKET */652653#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */654655/* Bit masks for USB_TXCSR */656657#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */658#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */659#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */660#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */661#define STALL_SEND_T 0x10 /* issue a Stall handshake */662#define STALL_SENT_T 0x20 /* Stall handshake transmitted */663#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */664#define INCOMPTX_T 0x80 /* indicates that a large packet is split */665#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */666#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */667#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */668#define ISO_T 0x4000 /* enable Isochronous transfers */669#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */670#define ERROR_TH 0x4 /* error condition host mode */671#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */672#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */673674/* Bit masks for USB_TXCOUNT */675676#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */677678/* Bit masks for USB_RXCSR */679680#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */681#define FIFO_FULL_R 0x2 /* FIFO not empty */682#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */683#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */684#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */685#define STALL_SEND_R 0x20 /* issue a Stall handshake */686#define STALL_SENT_R 0x40 /* Stall handshake transmitted */687#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */688#define INCOMPRX_R 0x100 /* indicates that a large packet is split */689#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */690#define DISNYET_R 0x1000 /* disable Nyet handshakes */691#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */692#define ISO_R 0x4000 /* enable Isochronous transfers */693#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */694#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */695#define REQPKT_RH 0x20 /* request an IN transaction host mode */696#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */697#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */698#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */699#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */700701/* Bit masks for USB_RXCOUNT */702703#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */704705/* Bit masks for USB_TXTYPE */706707#define TARGET_EP_NO_T 0xf /* EP number */708#define PROTOCOL_T 0xc /* transfer type */709710/* Bit masks for USB_TXINTERVAL */711712#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */713714/* Bit masks for USB_RXTYPE */715716#define TARGET_EP_NO_R 0xf /* EP number */717#define PROTOCOL_R 0xc /* transfer type */718719/* Bit masks for USB_RXINTERVAL */720721#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */722723/* Bit masks for USB_DMA_INTERRUPT */724725#define DMA0_INT 0x1 /* DMA0 pending interrupt */726#define DMA1_INT 0x2 /* DMA1 pending interrupt */727#define DMA2_INT 0x4 /* DMA2 pending interrupt */728#define DMA3_INT 0x8 /* DMA3 pending interrupt */729#define DMA4_INT 0x10 /* DMA4 pending interrupt */730#define DMA5_INT 0x20 /* DMA5 pending interrupt */731#define DMA6_INT 0x40 /* DMA6 pending interrupt */732#define DMA7_INT 0x80 /* DMA7 pending interrupt */733734/* Bit masks for USB_DMAxCONTROL */735736#define DMA_ENA 0x1 /* DMA enable */737#define DIRECTION 0x2 /* direction of DMA transfer */738#define MODE 0x4 /* DMA Bus error */739#define INT_ENA 0x8 /* Interrupt enable */740#define EPNUM 0xf0 /* EP number */741#define BUSERROR 0x100 /* DMA Bus error */742743/* Bit masks for USB_DMAxADDRHIGH */744745#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */746747/* Bit masks for USB_DMAxADDRLOW */748749#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */750751/* Bit masks for USB_DMAxCOUNTHIGH */752753#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */754755/* Bit masks for USB_DMAxCOUNTLOW */756757#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */758759760/* ******************************************* */761/* MULTI BIT MACRO ENUMERATIONS */762/* ******************************************* */763764765#endif /* _DEF_BF542_H */766767768