Path: blob/master/arch/blackfin/mach-bf548/include/mach/defBF549.h
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/*1* Copyright 2007-2010 Analog Devices Inc.2*3* Licensed under the ADI BSD license or the GPL-2 (or later)4*/56#ifndef _DEF_BF549_H7#define _DEF_BF549_H89/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */10#include "defBF54x_base.h"1112/* The BF549 is like the BF544, but has MXVR */13#include "defBF547.h"1415/* MXVR Registers */1617#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */18#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */19#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */20#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */21#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */22#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */23#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */24#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */25#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */26#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */27#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */28#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */29#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */30#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */3132/* MXVR Allocation Table Registers */3334#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */35#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */36#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */37#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */38#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */39#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */40#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */41#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */42#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */43#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */44#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */45#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */46#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */47#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */48#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */4950/* MXVR Channel Assign Registers */5152#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */53#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */54#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */55#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */56#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */57#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */58#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */59#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */6061/* MXVR DMA0 Registers */6263#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */64#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */65#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */66#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */67#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */6869/* MXVR DMA1 Registers */7071#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */72#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */73#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */74#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */75#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */7677/* MXVR DMA2 Registers */7879#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */80#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */81#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */82#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */83#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */8485/* MXVR DMA3 Registers */8687#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */88#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */89#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */90#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */91#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */9293/* MXVR DMA4 Registers */9495#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */96#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */97#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */98#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */99#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */100101/* MXVR DMA5 Registers */102103#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */104#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */105#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */106#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */107#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */108109/* MXVR DMA6 Registers */110111#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */112#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */113#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */114#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */115#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */116117/* MXVR DMA7 Registers */118119#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */120#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */121#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */122#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */123#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */124125/* MXVR Asynch Packet Registers */126127#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */128#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */129#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */130#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */131#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */132133/* MXVR Control Message Registers */134135#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */136#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */137#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */138#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */139#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */140141/* MXVR Remote Read Registers */142143#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */144#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */145146/* MXVR Pattern Data Registers */147148#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */149#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */150#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */151#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */152153/* MXVR Frame Counter Registers */154155#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */156#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */157158/* MXVR Routing Table Registers */159160#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */161#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */162#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */163#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */164#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */165#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */166#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */167#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */168#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */169#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */170#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */171#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */172#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */173#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */174#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */175176/* MXVR Counter-Clock-Control Registers */177178#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */179#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */180#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */181#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */182#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */183#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */184185#endif /* _DEF_BF549_H */186187188