Path: blob/master/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
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/*1* Copyright 2007-2010 Analog Devices Inc.2*3* Licensed under the ADI BSD license or the GPL-2 (or later)4*/56#ifndef _DEF_BF54X_H7#define _DEF_BF54X_H8910/* ************************************************************** */11/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */12/* ************************************************************** */1314/* PLL Registers */1516#define PLL_CTL 0xffc00000 /* PLL Control Register */17#define PLL_DIV 0xffc00004 /* PLL Divisor Register */18#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */19#define PLL_STAT 0xffc0000c /* PLL Status Register */20#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */2122/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */2324#define CHIPID 0xffc0001425/* CHIPID Masks */26#define CHIPID_VERSION 0xF000000027#define CHIPID_FAMILY 0x0FFFF00028#define CHIPID_MANUFACTURE 0x00000FFE2930/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */3132#define SWRST 0xffc00100 /* Software Reset Register */33#define SYSCR 0xffc00104 /* System Configuration register */3435/* SIC Registers */3637#define SIC_RVECT 0xffc0010838#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */39#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */40#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */41#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */42#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */43#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */44#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */45#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */46#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */47#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */48#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */49#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */50#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */51#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */52#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */53#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */54#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */55#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */56#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */57#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */58#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */5960/* Watchdog Timer Registers */6162#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */63#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */64#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */6566/* RTC Registers */6768#define RTC_STAT 0xffc00300 /* RTC Status Register */69#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */70#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */71#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */72#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */73#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */7475/* UART0 Registers */7677#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */78#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */79#define UART0_GCTL 0xffc00408 /* Global Control Register */80#define UART0_LCR 0xffc0040c /* Line Control Register */81#define UART0_MCR 0xffc00410 /* Modem Control Register */82#define UART0_LSR 0xffc00414 /* Line Status Register */83#define UART0_MSR 0xffc00418 /* Modem Status Register */84#define UART0_SCR 0xffc0041c /* Scratch Register */85#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */86#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */87#define UART0_THR 0xffc00428 /* Transmit Hold Register */88#define UART0_RBR 0xffc0042c /* Receive Buffer Register */8990/* SPI0 Registers */9192#define SPI0_REGBASE 0xffc0050093#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */94#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */95#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */96#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */97#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */98#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */99#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */100101/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */102103/* Two Wire Interface Registers (TWI0) */104105#define TWI0_REGBASE 0xffc00700106#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */107#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */108#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */109#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */110#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */111#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */112#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */113#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */114#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */115#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */116#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */117#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */118#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */119#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */120#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */121#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */122123/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */124125/* SPORT1 Registers */126127#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */128#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */129#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */130#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */131#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */132#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */133#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */134#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */135#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */136#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */137#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */138#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */139#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */140#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */141#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */142#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */143#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */144#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */145#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */146#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */147#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */148#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */149150/* Asynchronous Memory Control Registers */151152#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */153#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */154#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */155#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */156#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */157#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */158#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */159160/* DDR Memory Control Registers */161162#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */163#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */164#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */165#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */166#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */167#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */168#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */169#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */170171/* DDR BankRead and Write Count Registers */172173#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */174#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */175#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */176#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */177#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */178#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */179#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */180#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */181#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */182#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */183#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */184#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */185#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */186#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */187#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */188#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */189#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */190#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */191#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */192#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */193#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */194#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */195#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */196#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */197#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */198199/* DMAC0 Registers */200201#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */202#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */203204/* DMA Channel 0 Registers */205206#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */207#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */208#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */209#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */210#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */211#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */212#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */213#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */214#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */215#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */216#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */217#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */218#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */219220/* DMA Channel 1 Registers */221222#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */223#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */224#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */225#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */226#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */227#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */228#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */229#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */230#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */231#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */232#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */233#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */234#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */235236/* DMA Channel 2 Registers */237238#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */239#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */240#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */241#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */242#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */243#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */244#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */245#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */246#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */247#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */248#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */249#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */250#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */251252/* DMA Channel 3 Registers */253254#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */255#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */256#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */257#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */258#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */259#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */260#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */261#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */262#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */263#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */264#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */265#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */266#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */267268/* DMA Channel 4 Registers */269270#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */271#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */272#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */273#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */274#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */275#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */276#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */277#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */278#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */279#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */280#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */281#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */282#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */283284/* DMA Channel 5 Registers */285286#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */287#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */288#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */289#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */290#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */291#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */292#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */293#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */294#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */295#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */296#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */297#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */298#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */299300/* DMA Channel 6 Registers */301302#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */303#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */304#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */305#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */306#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */307#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */308#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */309#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */310#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */311#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */312#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */313#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */314#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */315316/* DMA Channel 7 Registers */317318#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */319#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */320#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */321#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */322#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */323#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */324#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */325#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */326#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */327#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */328#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */329#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */330#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */331332/* DMA Channel 8 Registers */333334#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */335#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */336#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */337#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */338#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */339#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */340#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */341#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */342#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */343#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */344#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */345#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */346#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */347348/* DMA Channel 9 Registers */349350#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */351#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */352#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */353#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */354#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */355#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */356#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */357#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */358#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */359#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */360#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */361#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */362#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */363364/* DMA Channel 10 Registers */365366#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */367#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */368#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */369#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */370#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */371#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */372#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */373#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */374#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */375#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */376#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */377#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */378#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */379380/* DMA Channel 11 Registers */381382#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */383#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */384#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */385#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */386#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */387#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */388#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */389#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */390#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */391#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */392#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */393#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */394#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */395396/* MDMA Stream 0 Registers */397398#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */399#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */400#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */401#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */402#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */403#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */404#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */405#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */406#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */407#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */408#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */409#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */410#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */411#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */412#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */413#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */414#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */415#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */416#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */417#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */418#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */419#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */420#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */421#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */422#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */423#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */424425/* MDMA Stream 1 Registers */426427#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */428#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */429#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */430#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */431#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */432#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */433#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */434#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */435#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */436#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */437#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */438#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */439#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */440#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */441#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */442#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */443#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */444#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */445#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */446#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */447#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */448#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */449#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */450#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */451#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */452#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */453454/* UART3 Registers */455456#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */457#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */458#define UART3_GCTL 0xffc03108 /* Global Control Register */459#define UART3_LCR 0xffc0310c /* Line Control Register */460#define UART3_MCR 0xffc03110 /* Modem Control Register */461#define UART3_LSR 0xffc03114 /* Line Status Register */462#define UART3_MSR 0xffc03118 /* Modem Status Register */463#define UART3_SCR 0xffc0311c /* Scratch Register */464#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */465#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */466#define UART3_THR 0xffc03128 /* Transmit Hold Register */467#define UART3_RBR 0xffc0312c /* Receive Buffer Register */468469/* EPPI1 Registers */470471#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */472#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */473#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */474#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */475#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */476#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */477#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */478#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */479#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */480#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */481#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */482#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */483#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */484#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */485486/* Port Interrupt 0 Registers (32-bit) */487488#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */489#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */490#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */491#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */492#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */493#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */494#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */495#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */496#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */497#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */498499/* Port Interrupt 1 Registers (32-bit) */500501#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */502#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */503#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */504#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */505#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */506#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */507#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */508#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */509#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */510#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */511512/* Port Interrupt 2 Registers (32-bit) */513514#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */515#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */516#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */517#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */518#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */519#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */520#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */521#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */522#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */523#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */524525/* Port Interrupt 3 Registers (32-bit) */526527#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */528#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */529#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */530#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */531#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */532#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */533#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */534#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */535#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */536#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */537538/* Port A Registers */539540#define PORTA_FER 0xffc014c0 /* Function Enable Register */541#define PORTA 0xffc014c4 /* GPIO Data Register */542#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */543#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */544#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */545#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */546#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */547#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */548549/* Port B Registers */550551#define PORTB_FER 0xffc014e0 /* Function Enable Register */552#define PORTB 0xffc014e4 /* GPIO Data Register */553#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */554#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */555#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */556#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */557#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */558#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */559560/* Port C Registers */561562#define PORTC_FER 0xffc01500 /* Function Enable Register */563#define PORTC 0xffc01504 /* GPIO Data Register */564#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */565#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */566#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */567#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */568#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */569#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */570571/* Port D Registers */572573#define PORTD_FER 0xffc01520 /* Function Enable Register */574#define PORTD 0xffc01524 /* GPIO Data Register */575#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */576#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */577#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */578#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */579#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */580#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */581582/* Port E Registers */583584#define PORTE_FER 0xffc01540 /* Function Enable Register */585#define PORTE 0xffc01544 /* GPIO Data Register */586#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */587#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */588#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */589#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */590#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */591#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */592593/* Port F Registers */594595#define PORTF_FER 0xffc01560 /* Function Enable Register */596#define PORTF 0xffc01564 /* GPIO Data Register */597#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */598#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */599#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */600#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */601#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */602#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */603604/* Port G Registers */605606#define PORTG_FER 0xffc01580 /* Function Enable Register */607#define PORTG 0xffc01584 /* GPIO Data Register */608#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */609#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */610#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */611#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */612#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */613#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */614615/* Port H Registers */616617#define PORTH_FER 0xffc015a0 /* Function Enable Register */618#define PORTH 0xffc015a4 /* GPIO Data Register */619#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */620#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */621#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */622#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */623#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */624#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */625626/* Port I Registers */627628#define PORTI_FER 0xffc015c0 /* Function Enable Register */629#define PORTI 0xffc015c4 /* GPIO Data Register */630#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */631#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */632#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */633#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */634#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */635#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */636637/* Port J Registers */638639#define PORTJ_FER 0xffc015e0 /* Function Enable Register */640#define PORTJ 0xffc015e4 /* GPIO Data Register */641#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */642#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */643#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */644#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */645#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */646#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */647648/* PWM Timer Registers */649650#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */651#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */652#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */653#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */654#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */655#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */656#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */657#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */658#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */659#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */660#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */661#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */662#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */663#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */664#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */665#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */666#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */667#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */668#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */669#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */670#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */671#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */672#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */673#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */674#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */675#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */676#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */677#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */678#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */679#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */680#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */681#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */682683/* Timer Group of 8 */684685#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */686#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */687#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */688689/* DMAC1 Registers */690691#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */692#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */693694/* DMA Channel 12 Registers */695696#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */697#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */698#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */699#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */700#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */701#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */702#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */703#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */704#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */705#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */706#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */707#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */708#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */709710/* DMA Channel 13 Registers */711712#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */713#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */714#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */715#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */716#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */717#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */718#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */719#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */720#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */721#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */722#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */723#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */724#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */725726/* DMA Channel 14 Registers */727728#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */729#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */730#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */731#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */732#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */733#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */734#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */735#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */736#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */737#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */738#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */739#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */740#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */741742/* DMA Channel 15 Registers */743744#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */745#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */746#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */747#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */748#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */749#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */750#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */751#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */752#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */753#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */754#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */755#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */756#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */757758/* DMA Channel 16 Registers */759760#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */761#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */762#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */763#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */764#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */765#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */766#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */767#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */768#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */769#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */770#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */771#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */772#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */773774/* DMA Channel 17 Registers */775776#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */777#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */778#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */779#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */780#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */781#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */782#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */783#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */784#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */785#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */786#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */787#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */788#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */789790/* DMA Channel 18 Registers */791792#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */793#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */794#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */795#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */796#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */797#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */798#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */799#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */800#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */801#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */802#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */803#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */804#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */805806/* DMA Channel 19 Registers */807808#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */809#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */810#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */811#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */812#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */813#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */814#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */815#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */816#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */817#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */818#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */819#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */820#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */821822/* DMA Channel 20 Registers */823824#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */825#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */826#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */827#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */828#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */829#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */830#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */831#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */832#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */833#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */834#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */835#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */836#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */837838/* DMA Channel 21 Registers */839840#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */841#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */842#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */843#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */844#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */845#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */846#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */847#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */848#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */849#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */850#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */851#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */852#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */853854/* DMA Channel 22 Registers */855856#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */857#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */858#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */859#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */860#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */861#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */862#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */863#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */864#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */865#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */866#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */867#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */868#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */869870/* DMA Channel 23 Registers */871872#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */873#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */874#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */875#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */876#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */877#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */878#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */879#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */880#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */881#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */882#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */883#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */884#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */885886/* MDMA Stream 2 Registers */887888#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */889#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */890#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */891#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */892#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */893#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */894#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */895#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */896#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */897#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */898#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */899#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */900#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */901#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */902#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */903#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */904#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */905#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */906#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */907#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */908#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */909#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */910#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */911#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */912#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */913#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */914915/* MDMA Stream 3 Registers */916917#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */918#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */919#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */920#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */921#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */922#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */923#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */924#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */925#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */926#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */927#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */928#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */929#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */930#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */931#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */932#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */933#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */934#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */935#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */936#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */937#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */938#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */939#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */940#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */941#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */942#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */943944/* UART1 Registers */945946#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */947#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */948#define UART1_GCTL 0xffc02008 /* Global Control Register */949#define UART1_LCR 0xffc0200c /* Line Control Register */950#define UART1_MCR 0xffc02010 /* Modem Control Register */951#define UART1_LSR 0xffc02014 /* Line Status Register */952#define UART1_MSR 0xffc02018 /* Modem Status Register */953#define UART1_SCR 0xffc0201c /* Scratch Register */954#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */955#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */956#define UART1_THR 0xffc02028 /* Transmit Hold Register */957#define UART1_RBR 0xffc0202c /* Receive Buffer Register */958959/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */960961/* SPI1 Registers */962963#define SPI1_REGBASE 0xffc02300964#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */965#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */966#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */967#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */968#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */969#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */970#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */971972/* SPORT2 Registers */973974#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */975#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */976#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */977#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */978#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */979#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */980#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */981#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */982#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */983#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */984#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */985#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */986#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */987#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */988#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */989#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */990#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */991#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */992#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */993#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */994#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */995#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */996997/* SPORT3 Registers */998999#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */1000#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */1001#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */1002#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */1003#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */1004#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */1005#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */1006#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */1007#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */1008#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */1009#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */1010#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */1011#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */1012#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */1013#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */1014#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */1015#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */1016#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */1017#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */1018#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */1019#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */1020#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */10211022/* EPPI2 Registers */10231024#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */1025#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */1026#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */1027#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */1028#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */1029#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */1030#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */1031#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */1032#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */1033#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */1034#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */1035#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */1036#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */1037#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */10381039/* CAN Controller 0 Config 1 Registers */10401041#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */1042#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */1043#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */1044#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */1045#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */1046#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */1047#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */1048#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */1049#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */1050#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */1051#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */1052#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */1053#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */10541055/* CAN Controller 0 Config 2 Registers */10561057#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */1058#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */1059#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */1060#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */1061#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */1062#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */1063#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */1064#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */1065#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */1066#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */1067#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */1068#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */1069#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */10701071/* CAN Controller 0 Clock/Interrupt/Counter Registers */10721073#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */1074#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */1075#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */1076#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */1077#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */1078#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */1079#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */1080#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */1081#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */1082#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */1083#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */1084#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */1085#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */1086#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */1087#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */1088#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */10891090/* CAN Controller 0 Acceptance Registers */10911092#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */1093#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */1094#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */1095#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */1096#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */1097#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */1098#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */1099#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */1100#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */1101#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */1102#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */1103#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */1104#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */1105#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */1106#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */1107#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */1108#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */1109#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */1110#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */1111#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */1112#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */1113#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */1114#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */1115#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */1116#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */1117#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */1118#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */1119#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */1120#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */1121#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */1122#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */1123#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */11241125/* CAN Controller 0 Acceptance Registers */11261127#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */1128#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */1129#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */1130#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */1131#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */1132#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */1133#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */1134#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */1135#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */1136#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */1137#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */1138#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */1139#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */1140#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */1141#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */1142#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */1143#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */1144#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */1145#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */1146#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */1147#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */1148#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */1149#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */1150#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */1151#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */1152#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */1153#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */1154#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */1155#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */1156#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */1157#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */1158#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */11591160/* CAN Controller 0 Mailbox Data Registers */11611162#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */1163#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */1164#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */1165#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */1166#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */1167#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */1168#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */1169#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */1170#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */1171#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */1172#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */1173#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */1174#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */1175#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */1176#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */1177#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */1178#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */1179#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */1180#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */1181#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */1182#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */1183#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */1184#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */1185#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */1186#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */1187#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */1188#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */1189#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */1190#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */1191#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */1192#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */1193#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */1194#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */1195#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */1196#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */1197#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */1198#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */1199#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */1200#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */1201#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */1202#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */1203#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */1204#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */1205#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */1206#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */1207#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */1208#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */1209#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */1210#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */1211#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */1212#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */1213#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */1214#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */1215#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */1216#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */1217#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */1218#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */1219#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */1220#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */1221#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */1222#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */1223#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */1224#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */1225#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */1226#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */1227#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */1228#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */1229#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */1230#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */1231#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */1232#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */1233#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */1234#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */1235#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */1236#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */1237#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */1238#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */1239#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */1240#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */1241#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */1242#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */1243#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */1244#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */1245#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */1246#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */1247#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */1248#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */1249#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */1250#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */1251#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */1252#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */1253#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */1254#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */1255#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */1256#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */1257#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */1258#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */1259#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */1260#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */1261#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */1262#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */1263#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */1264#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */1265#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */1266#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */1267#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */1268#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */1269#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */1270#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */1271#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */1272#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */1273#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */1274#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */1275#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */1276#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */1277#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */1278#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */1279#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */1280#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */1281#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */1282#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */1283#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */1284#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */1285#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */1286#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */1287#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */1288#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */1289#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */12901291/* CAN Controller 0 Mailbox Data Registers */12921293#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */1294#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */1295#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */1296#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */1297#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */1298#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */1299#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */1300#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */1301#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */1302#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */1303#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */1304#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */1305#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */1306#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */1307#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */1308#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */1309#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */1310#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */1311#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */1312#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */1313#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */1314#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */1315#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */1316#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */1317#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */1318#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */1319#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */1320#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */1321#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */1322#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */1323#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */1324#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */1325#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */1326#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */1327#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */1328#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */1329#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */1330#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */1331#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */1332#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */1333#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */1334#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */1335#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */1336#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */1337#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */1338#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */1339#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */1340#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */1341#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */1342#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */1343#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */1344#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */1345#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */1346#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */1347#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */1348#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */1349#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */1350#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */1351#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */1352#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */1353#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */1354#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */1355#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */1356#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */1357#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */1358#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */1359#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */1360#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */1361#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */1362#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */1363#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */1364#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */1365#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */1366#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */1367#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */1368#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */1369#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */1370#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */1371#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */1372#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */1373#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */1374#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */1375#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */1376#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */1377#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */1378#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */1379#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */1380#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */1381#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */1382#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */1383#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */1384#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */1385#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */1386#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */1387#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */1388#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */1389#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */1390#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */1391#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */1392#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */1393#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */1394#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */1395#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */1396#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */1397#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */1398#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */1399#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */1400#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */1401#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */1402#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */1403#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */1404#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */1405#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */1406#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */1407#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */1408#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */1409#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */1410#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */1411#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */1412#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */1413#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */1414#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */1415#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */1416#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */1417#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */1418#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */1419#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */1420#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */14211422/* UART3 Registers */14231424#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */1425#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */1426#define UART3_GCTL 0xffc03108 /* Global Control Register */1427#define UART3_LCR 0xffc0310c /* Line Control Register */1428#define UART3_MCR 0xffc03110 /* Modem Control Register */1429#define UART3_LSR 0xffc03114 /* Line Status Register */1430#define UART3_MSR 0xffc03118 /* Modem Status Register */1431#define UART3_SCR 0xffc0311c /* Scratch Register */1432#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */1433#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */1434#define UART3_THR 0xffc03128 /* Transmit Hold Register */1435#define UART3_RBR 0xffc0312c /* Receive Buffer Register */14361437/* NFC Registers */14381439#define NFC_CTL 0xffc03b00 /* NAND Control Register */1440#define NFC_STAT 0xffc03b04 /* NAND Status Register */1441#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */1442#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */1443#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */1444#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */1445#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */1446#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */1447#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */1448#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */1449#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */1450#define NFC_READ 0xffc03b2c /* NAND Read Data Register */1451#define NFC_ADDR 0xffc03b40 /* NAND Address Register */1452#define NFC_CMD 0xffc03b44 /* NAND Command Register */1453#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */1454#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */14551456/* Counter Registers */14571458#define CNT_CONFIG 0xffc04200 /* Configuration Register */1459#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */1460#define CNT_STATUS 0xffc04208 /* Status Register */1461#define CNT_COMMAND 0xffc0420c /* Command Register */1462#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */1463#define CNT_COUNTER 0xffc04214 /* Counter Register */1464#define CNT_MAX 0xffc04218 /* Maximal Count Register */1465#define CNT_MIN 0xffc0421c /* Minimal Count Register */14661467/* OTP/FUSE Registers */14681469#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */1470#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */1471#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */1472#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */14731474/* Security Registers */14751476#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */1477#define SECURE_CONTROL 0xffc04324 /* Secure Control */1478#define SECURE_STATUS 0xffc04328 /* Secure Status */14791480/* DMA Peripheral Mux Register */14811482#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */14831484/* OTP Read/Write Data Buffer Registers */14851486#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */1487#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */1488#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */1489#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */14901491/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */14921493/* ********************************************************** */1494/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */1495/* and MULTI BIT READ MACROS */1496/* ********************************************************** */14971498/* SIC_IMASK Masks */1499#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */1500#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */1501#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */1502#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */15031504/* SIC_IWR Masks */1505#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */1506#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */1507#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */1508#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */15091510/* Bit masks for SIC_IAR0 */15111512#define PLL_WAKEUP 0x1 /* PLL Wakeup */15131514/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */15151516#define DMA0_ERR 0x2 /* DMA Controller 0 Error */1517#define EPPI0_ERR 0x4 /* EPPI0 Error */1518#define SPORT0_ERR 0x8 /* SPORT0 Error */1519#define SPORT1_ERR 0x10 /* SPORT1 Error */1520#define SPI0_ERR 0x20 /* SPI0 Error */1521#define UART0_ERR 0x40 /* UART0 Error */1522#define RTC 0x80 /* Real-Time Clock */1523#define DMA12 0x100 /* DMA Channel 12 */1524#define DMA0 0x200 /* DMA Channel 0 */1525#define DMA1 0x400 /* DMA Channel 1 */1526#define DMA2 0x800 /* DMA Channel 2 */1527#define DMA3 0x1000 /* DMA Channel 3 */1528#define DMA4 0x2000 /* DMA Channel 4 */1529#define DMA6 0x4000 /* DMA Channel 6 */1530#define DMA7 0x8000 /* DMA Channel 7 */1531#define PINT0 0x80000 /* Pin Interrupt 0 */1532#define PINT1 0x100000 /* Pin Interrupt 1 */1533#define MDMA0 0x200000 /* Memory DMA Stream 0 */1534#define MDMA1 0x400000 /* Memory DMA Stream 1 */1535#define WDOG 0x800000 /* Watchdog Timer */1536#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */1537#define SPORT2_ERR 0x2000000 /* SPORT2 Error */1538#define SPORT3_ERR 0x4000000 /* SPORT3 Error */1539#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */1540#define SPI1_ERR 0x10000000 /* SPI1 Error */1541#define SPI2_ERR 0x20000000 /* SPI2 Error */1542#define UART1_ERR 0x40000000 /* UART1 Error */1543#define UART2_ERR 0x80000000 /* UART2 Error */15441545/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */15461547#define CAN0_ERR 0x1 /* CAN0 Error */1548#define DMA18 0x2 /* DMA Channel 18 */1549#define DMA19 0x4 /* DMA Channel 19 */1550#define DMA20 0x8 /* DMA Channel 20 */1551#define DMA21 0x10 /* DMA Channel 21 */1552#define DMA13 0x20 /* DMA Channel 13 */1553#define DMA14 0x40 /* DMA Channel 14 */1554#define DMA5 0x80 /* DMA Channel 5 */1555#define DMA23 0x100 /* DMA Channel 23 */1556#define DMA8 0x200 /* DMA Channel 8 */1557#define DMA9 0x400 /* DMA Channel 9 */1558#define DMA10 0x800 /* DMA Channel 10 */1559#define DMA11 0x1000 /* DMA Channel 11 */1560#define TWI0 0x2000 /* TWI0 */1561#define TWI1 0x4000 /* TWI1 */1562#define CAN0_RX 0x8000 /* CAN0 Receive */1563#define CAN0_TX 0x10000 /* CAN0 Transmit */1564#define MDMA2 0x20000 /* Memory DMA Stream 0 */1565#define MDMA3 0x40000 /* Memory DMA Stream 1 */1566#define MXVR_STAT 0x80000 /* MXVR Status */1567#define MXVR_CM 0x100000 /* MXVR Control Message */1568#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */1569#define EPPI1_ERR 0x400000 /* EPPI1 Error */1570#define EPPI2_ERR 0x800000 /* EPPI2 Error */1571#define UART3_ERR 0x1000000 /* UART3 Error */1572#define HOST_ERR 0x2000000 /* Host DMA Port Error */1573#define USB_ERR 0x4000000 /* USB Error */1574#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */1575#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */1576#define ATAPI_ERR 0x20000000 /* ATAPI Error */1577#define CAN1_ERR 0x40000000 /* CAN1 Error */1578#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */1579#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */1580#define DMAR0 0x80000000 /* DMAR0 Block */1581#define DMAR1 0x80000000 /* DMAR1 Block */15821583/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */15841585#define DMA15 0x1 /* DMA Channel 15 */1586#define DMA16 0x2 /* DMA Channel 16 */1587#define DMA17 0x4 /* DMA Channel 17 */1588#define DMA22 0x8 /* DMA Channel 22 */1589#define CNT 0x10 /* Counter */1590#define KEY 0x20 /* Keypad */1591#define CAN1_RX 0x40 /* CAN1 Receive */1592#define CAN1_TX 0x80 /* CAN1 Transmit */1593#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */1594#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */1595#define USB_EINT 0x400 /* USB Exception */1596#define USB_INT0 0x800 /* USB Interrupt 0 */1597#define USB_INT1 0x1000 /* USB Interrupt 1 */1598#define USB_INT2 0x2000 /* USB Interrupt 2 */1599#define USB_DMAINT 0x4000 /* USB DMA */1600#define OTPSEC 0x8000 /* OTP Access Complete */1601#define TIMER0 0x400000 /* Timer 0 */1602#define TIMER1 0x800000 /* Timer 1 */1603#define TIMER2 0x1000000 /* Timer 2 */1604#define TIMER3 0x2000000 /* Timer 3 */1605#define TIMER4 0x4000000 /* Timer 4 */1606#define TIMER5 0x8000000 /* Timer 5 */1607#define TIMER6 0x10000000 /* Timer 6 */1608#define TIMER7 0x20000000 /* Timer 7 */1609#define PINT2 0x40000000 /* Pin Interrupt 2 */1610#define PINT3 0x80000000 /* Pin Interrupt 3 */16111612/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */16131614#define CTYPE 0x40 /* DMA Channel Type */1615#define PMAP 0xf000 /* Peripheral Mapped To This Channel */16161617/* Bit masks for DMACx_TC_PER */16181619#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */1620#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */1621#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */1622#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */16231624/* Bit masks for DMACx_TC_CNT */16251626#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */1627#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */1628#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */1629#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */16301631/* Bit masks for DMAC1_PERIMUX */16321633#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */16341635/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/1636/* EBIU_AMGCTL Masks */1637#define AMCKEN 0x0001 /* Enable CLKOUT */1638#define AMBEN_NONE 0x0000 /* All Banks Disabled */1639#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */1640#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */1641#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */1642#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */164316441645/* Bit masks for EBIU_AMBCTL0 */16461647#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */1648#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */1649#define B0TT 0xc /* Bank 0 transition time */1650#define B0ST 0x30 /* Bank 0 Setup time */1651#define B0HT 0xc0 /* Bank 0 Hold time */1652#define B0RAT 0xf00 /* Bank 0 Read access time */1653#define B0WAT 0xf000 /* Bank 0 write access time */1654#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */1655#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */1656#define B1TT 0xc0000 /* Bank 1 transition time */1657#define B1ST 0x300000 /* Bank 1 Setup time */1658#define B1HT 0xc00000 /* Bank 1 Hold time */1659#define B1RAT 0xf000000 /* Bank 1 Read access time */1660#define B1WAT 0xf0000000 /* Bank 1 write access time */16611662/* Bit masks for EBIU_AMBCTL1 */16631664#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */1665#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */1666#define B2TT 0xc /* Bank 2 transition time */1667#define B2ST 0x30 /* Bank 2 Setup time */1668#define B2HT 0xc0 /* Bank 2 Hold time */1669#define B2RAT 0xf00 /* Bank 2 Read access time */1670#define B2WAT 0xf000 /* Bank 2 write access time */1671#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */1672#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */1673#define B3TT 0xc0000 /* Bank 3 transition time */1674#define B3ST 0x300000 /* Bank 3 Setup time */1675#define B3HT 0xc00000 /* Bank 3 Hold time */1676#define B3RAT 0xf000000 /* Bank 3 Read access time */1677#define B3WAT 0xf0000000 /* Bank 3 write access time */16781679/* Bit masks for EBIU_MBSCTL */16801681#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */1682#define AMSB1CTL 0xc /* Async Memory Bank 1 select */1683#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */1684#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */16851686/* Bit masks for EBIU_MODE */16871688#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */1689#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */1690#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */1691#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */16921693/* Bit masks for EBIU_FCTL */16941695#define TESTSETLOCK 0x1 /* Test set lock */1696#define BCLK 0x6 /* Burst clock frequency */1697#define PGWS 0x38 /* Page wait states */1698#define PGSZ 0x40 /* Page size */1699#define RDDL 0x380 /* Read data delay */17001701/* Bit masks for EBIU_ARBSTAT */17021703#define ARBSTAT 0x1 /* Arbitration status */1704#define BGSTAT 0x2 /* Bus grant status */17051706/* Bit masks for EBIU_DDRCTL0 */17071708#define TREFI 0x3fff /* Refresh Interval */1709#define TRFC 0x3c000 /* Auto-refresh command period */1710#define TRP 0x3c0000 /* Pre charge-to-active command period */1711#define TRAS 0x3c00000 /* Min Active-to-pre charge time */1712#define TRC 0x3c000000 /* Active-to-active time */1713#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */1714#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */1715#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */1716#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */1717#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */17181719/* Bit masks for EBIU_DDRCTL1 */17201721#define TRCD 0xf /* Active-to-Read/write delay */1722#define TMRD 0xf0 /* Mode register set to active */1723#define TWR 0x300 /* Write Recovery time */1724#define DDRDATWIDTH 0x3000 /* DDR data width */1725#define EXTBANKS 0xc000 /* External banks */1726#define DDRDEVWIDTH 0x30000 /* DDR device width */1727#define DDRDEVSIZE 0xc0000 /* DDR device size */1728#define TWTR 0xf0000000 /* Write-to-read delay */1729#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */1730#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */1731#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */1732#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */1733#define DDR_DATWIDTH 0x2000 /* DDR data width */1734#define EXTBANK_1 0 /* 1 external bank */1735#define EXTBANK_2 0x4000 /* 2 external banks */1736#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */1737#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */1738#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */1739#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */1740#define DEVWD_4 0 /* DDR Device Width = 4 Bits */1741#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */1742#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */17431744/* Bit masks for EBIU_DDRCTL2 */17451746#define BURSTLENGTH 0x7 /* Burst length */1747#define CASLATENCY 0x70 /* CAS latency */1748#define DLLRESET 0x100 /* DLL Reset */1749#define REGE 0x1000 /* Register mode enable */1750#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */1751#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */1752#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */1753#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */17541755/* Bit masks for EBIU_DDRCTL3 */17561757#define PASR 0x7 /* Partial array self-refresh */17581759/* Bit masks for EBIU_DDRQUE */17601761#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */1762#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */1763#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */1764#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */1765#define DEB1_URGENT 0x1000 /* DEB1 Urgent */1766#define DEB2_URGENT 0x2000 /* DEB2 Urgent */1767#define DEB3_URGENT 0x4000 /* DEB3 Urgent */17681769/* Bit masks for EBIU_ERRMST */17701771#define DEB1_ERROR 0x1 /* DEB1 Error */1772#define DEB2_ERROR 0x2 /* DEB2 Error */1773#define DEB3_ERROR 0x4 /* DEB3 Error */1774#define CORE_ERROR 0x8 /* Core error */1775#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */1776#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */1777#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */1778#define CORE_MERROR 0x80 /* Core Error (2nd) */17791780/* Bit masks for EBIU_RSTCTL */17811782#define DDRSRESET 0x1 /* DDR soft reset */1783#define PFTCHSRESET 0x4 /* DDR prefetch reset */1784#define SRREQ 0x8 /* Self-refresh request */1785#define SRACK 0x10 /* Self-refresh acknowledge */1786#define MDDRENABLE 0x20 /* Mobile DDR enable */17871788/* Bit masks for EBIU_DDRMCEN */17891790#define B0WCENABLE 0x1 /* Bank 0 write count enable */1791#define B1WCENABLE 0x2 /* Bank 1 write count enable */1792#define B2WCENABLE 0x4 /* Bank 2 write count enable */1793#define B3WCENABLE 0x8 /* Bank 3 write count enable */1794#define B4WCENABLE 0x10 /* Bank 4 write count enable */1795#define B5WCENABLE 0x20 /* Bank 5 write count enable */1796#define B6WCENABLE 0x40 /* Bank 6 write count enable */1797#define B7WCENABLE 0x80 /* Bank 7 write count enable */1798#define B0RCENABLE 0x100 /* Bank 0 read count enable */1799#define B1RCENABLE 0x200 /* Bank 1 read count enable */1800#define B2RCENABLE 0x400 /* Bank 2 read count enable */1801#define B3RCENABLE 0x800 /* Bank 3 read count enable */1802#define B4RCENABLE 0x1000 /* Bank 4 read count enable */1803#define B5RCENABLE 0x2000 /* Bank 5 read count enable */1804#define B6RCENABLE 0x4000 /* Bank 6 read count enable */1805#define B7RCENABLE 0x8000 /* Bank 7 read count enable */1806#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */1807#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */1808#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */1809#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */1810#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */1811#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */1812#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */1813#define GCCONTROL 0x3000000 /* DDR Grant Count Control */18141815/* Bit masks for EBIU_DDRMCCL */18161817#define CB0WCOUNT 0x1 /* Clear write count 0 */1818#define CB1WCOUNT 0x2 /* Clear write count 1 */1819#define CB2WCOUNT 0x4 /* Clear write count 2 */1820#define CB3WCOUNT 0x8 /* Clear write count 3 */1821#define CB4WCOUNT 0x10 /* Clear write count 4 */1822#define CB5WCOUNT 0x20 /* Clear write count 5 */1823#define CB6WCOUNT 0x40 /* Clear write count 6 */1824#define CB7WCOUNT 0x80 /* Clear write count 7 */1825#define CBRCOUNT 0x100 /* Clear read count 0 */1826#define CB1RCOUNT 0x200 /* Clear read count 1 */1827#define CB2RCOUNT 0x400 /* Clear read count 2 */1828#define CB3RCOUNT 0x800 /* Clear read count 3 */1829#define CB4RCOUNT 0x1000 /* Clear read count 4 */1830#define CB5RCOUNT 0x2000 /* Clear read count 5 */1831#define CB6RCOUNT 0x4000 /* Clear read count 6 */1832#define CB7RCOUNT 0x8000 /* Clear read count 7 */1833#define CRACOUNT 0x10000 /* Clear row activation count */1834#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */1835#define CARCOUNT 0x40000 /* Clear auto-refresh count */1836#define CG0COUNT 0x100000 /* Clear grant count 0 */1837#define CG1COUNT 0x200000 /* Clear grant count 1 */1838#define CG2COUNT 0x400000 /* Clear grant count 2 */1839#define CG3COUNT 0x800000 /* Clear grant count 3 */18401841/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */18421843#define Px0 0x1 /* GPIO 0 */1844#define Px1 0x2 /* GPIO 1 */1845#define Px2 0x4 /* GPIO 2 */1846#define Px3 0x8 /* GPIO 3 */1847#define Px4 0x10 /* GPIO 4 */1848#define Px5 0x20 /* GPIO 5 */1849#define Px6 0x40 /* GPIO 6 */1850#define Px7 0x80 /* GPIO 7 */1851#define Px8 0x100 /* GPIO 8 */1852#define Px9 0x200 /* GPIO 9 */1853#define Px10 0x400 /* GPIO 10 */1854#define Px11 0x800 /* GPIO 11 */1855#define Px12 0x1000 /* GPIO 12 */1856#define Px13 0x2000 /* GPIO 13 */1857#define Px14 0x4000 /* GPIO 14 */1858#define Px15 0x8000 /* GPIO 15 */18591860/* Bit masks for PORTA_MUX - PORTJ_MUX */18611862#define PxM0 0x3 /* GPIO Mux 0 */1863#define PxM1 0xc /* GPIO Mux 1 */1864#define PxM2 0x30 /* GPIO Mux 2 */1865#define PxM3 0xc0 /* GPIO Mux 3 */1866#define PxM4 0x300 /* GPIO Mux 4 */1867#define PxM5 0xc00 /* GPIO Mux 5 */1868#define PxM6 0x3000 /* GPIO Mux 6 */1869#define PxM7 0xc000 /* GPIO Mux 7 */1870#define PxM8 0x30000 /* GPIO Mux 8 */1871#define PxM9 0xc0000 /* GPIO Mux 9 */1872#define PxM10 0x300000 /* GPIO Mux 10 */1873#define PxM11 0xc00000 /* GPIO Mux 11 */1874#define PxM12 0x3000000 /* GPIO Mux 12 */1875#define PxM13 0xc000000 /* GPIO Mux 13 */1876#define PxM14 0x30000000 /* GPIO Mux 14 */1877#define PxM15 0xc0000000 /* GPIO Mux 15 */187818791880/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */18811882#define IB0 0x1 /* Interrupt Bit 0 */1883#define IB1 0x2 /* Interrupt Bit 1 */1884#define IB2 0x4 /* Interrupt Bit 2 */1885#define IB3 0x8 /* Interrupt Bit 3 */1886#define IB4 0x10 /* Interrupt Bit 4 */1887#define IB5 0x20 /* Interrupt Bit 5 */1888#define IB6 0x40 /* Interrupt Bit 6 */1889#define IB7 0x80 /* Interrupt Bit 7 */1890#define IB8 0x100 /* Interrupt Bit 8 */1891#define IB9 0x200 /* Interrupt Bit 9 */1892#define IB10 0x400 /* Interrupt Bit 10 */1893#define IB11 0x800 /* Interrupt Bit 11 */1894#define IB12 0x1000 /* Interrupt Bit 12 */1895#define IB13 0x2000 /* Interrupt Bit 13 */1896#define IB14 0x4000 /* Interrupt Bit 14 */1897#define IB15 0x8000 /* Interrupt Bit 15 */18981899/* Bit masks for TIMERx_CONFIG */19001901#define TMODE 0x3 /* Timer Mode */1902#define PULSE_HI 0x4 /* Pulse Polarity */1903#define PERIOD_CNT 0x8 /* Period Count */1904#define IRQ_ENA 0x10 /* Interrupt Request Enable */1905#define TIN_SEL 0x20 /* Timer Input Select */1906#define OUT_DIS 0x40 /* Output Pad Disable */1907#define CLK_SEL 0x80 /* Timer Clock Select */1908#define TOGGLE_HI 0x100 /* Toggle Mode */1909#define EMU_RUN 0x200 /* Emulation Behavior Select */1910#define ERR_TYP 0xc000 /* Error Type */19111912/* Bit masks for TIMER_ENABLE0 */19131914#define TIMEN0 0x1 /* Timer 0 Enable */1915#define TIMEN1 0x2 /* Timer 1 Enable */1916#define TIMEN2 0x4 /* Timer 2 Enable */1917#define TIMEN3 0x8 /* Timer 3 Enable */1918#define TIMEN4 0x10 /* Timer 4 Enable */1919#define TIMEN5 0x20 /* Timer 5 Enable */1920#define TIMEN6 0x40 /* Timer 6 Enable */1921#define TIMEN7 0x80 /* Timer 7 Enable */19221923/* Bit masks for TIMER_DISABLE0 */19241925#define TIMDIS0 0x1 /* Timer 0 Disable */1926#define TIMDIS1 0x2 /* Timer 1 Disable */1927#define TIMDIS2 0x4 /* Timer 2 Disable */1928#define TIMDIS3 0x8 /* Timer 3 Disable */1929#define TIMDIS4 0x10 /* Timer 4 Disable */1930#define TIMDIS5 0x20 /* Timer 5 Disable */1931#define TIMDIS6 0x40 /* Timer 6 Disable */1932#define TIMDIS7 0x80 /* Timer 7 Disable */19331934/* Bit masks for TIMER_STATUS0 */19351936#define TIMIL0 0x1 /* Timer 0 Interrupt */1937#define TIMIL1 0x2 /* Timer 1 Interrupt */1938#define TIMIL2 0x4 /* Timer 2 Interrupt */1939#define TIMIL3 0x8 /* Timer 3 Interrupt */1940#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */1941#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */1942#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */1943#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */1944#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */1945#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */1946#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */1947#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */1948#define TIMIL4 0x10000 /* Timer 4 Interrupt */1949#define TIMIL5 0x20000 /* Timer 5 Interrupt */1950#define TIMIL6 0x40000 /* Timer 6 Interrupt */1951#define TIMIL7 0x80000 /* Timer 7 Interrupt */1952#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */1953#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */1954#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */1955#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */1956#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */1957#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */1958#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */1959#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */19601961/* Bit masks for SECURE_SYSSWT */19621963#define EMUDABL 0x1 /* Emulation Disable. */1964#define RSTDABL 0x2 /* Reset Disable */1965#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */1966#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */1967#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */1968#define DMA0OVR 0x800 /* DMA0 Memory Access Override */1969#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */1970#define EMUOVR 0x4000 /* Emulation Override */1971#define OTPSEN 0x8000 /* OTP Secrets Enable. */1972#define L2DABL 0x70000 /* L2 Memory Disable. */19731974/* Bit masks for SECURE_CONTROL */19751976#define SECURE0 0x1 /* SECURE 0 */1977#define SECURE1 0x2 /* SECURE 1 */1978#define SECURE2 0x4 /* SECURE 2 */1979#define SECURE3 0x8 /* SECURE 3 */19801981/* Bit masks for SECURE_STATUS */19821983#define SECMODE 0x3 /* Secured Mode Control State */1984#define NMI 0x4 /* Non Maskable Interrupt */1985#define AFVALID 0x8 /* Authentication Firmware Valid */1986#define AFEXIT 0x10 /* Authentication Firmware Exit */1987#define SECSTAT 0xe0 /* Secure Status */19881989/* SWRST Masks */1990#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */1991#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */1992#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */1993#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */1994#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */19951996/* Bit masks for EPPIx_STATUS */19971998#define CFIFO_ERR 0x1 /* Chroma FIFO Error */1999#define YFIFO_ERR 0x2 /* Luma FIFO Error */2000#define LTERR_OVR 0x4 /* Line Track Overflow */2001#define LTERR_UNDR 0x8 /* Line Track Underflow */2002#define FTERR_OVR 0x10 /* Frame Track Overflow */2003#define FTERR_UNDR 0x20 /* Frame Track Underflow */2004#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */2005#define DMA1URQ 0x80 /* DMA1 Urgent Request */2006#define DMA0URQ 0x100 /* DMA0 Urgent Request */2007#define ERR_DET 0x4000 /* Preamble Error Detected */2008#define FLD 0x8000 /* Field */20092010/* Bit masks for EPPIx_CONTROL */20112012#define EPPI_EN 0x1 /* Enable */2013#define EPPI_DIR 0x2 /* Direction */2014#define XFR_TYPE 0xc /* Operating Mode */2015#define FS_CFG 0x30 /* Frame Sync Configuration */2016#define FLD_SEL 0x40 /* Field Select/Trigger */2017#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */2018#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */2019#define ICLKGEN 0x200 /* Internal Clock Generation */2020#define IFSGEN 0x400 /* Internal Frame Sync Generation */2021#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */2022#define POLS 0x6000 /* Frame Sync Polarity */2023#define DLENGTH 0x38000 /* Data Length */2024#define SKIP_EN 0x40000 /* Skip Enable */2025#define SKIP_EO 0x80000 /* Skip Even or Odd */2026#define PACKEN 0x100000 /* Packing/Unpacking Enable */2027#define SWAPEN 0x200000 /* Swap Enable */2028#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */2029#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */2030#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */2031#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */2032#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */2033#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */2034#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */20352036#define DLEN_8 (0 << 15) /* 000 - 8 bits */2037#define DLEN_10 (1 << 15) /* 001 - 10 bits */2038#define DLEN_12 (2 << 15) /* 010 - 12 bits */2039#define DLEN_14 (3 << 15) /* 011 - 14 bits */2040#define DLEN_16 (4 << 15) /* 100 - 16 bits */2041#define DLEN_18 (5 << 15) /* 101 - 18 bits */2042#define DLEN_24 (6 << 15) /* 110 - 24 bits */204320442045/* Bit masks for EPPIx_FS2W_LVB */20462047#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */2048#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */2049#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */2050#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */20512052/* Bit masks for EPPIx_FS2W_LAVF */20532054#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */2055#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */20562057/* Bit masks for EPPIx_CLIP */20582059#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */2060#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */2061#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */2062#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */20632064/* ************************************************ */2065/* The TWI bit masks fields are from the ADSP-BF538 */2066/* and they have not been verified as the final */2067/* ones for the Moab processors ... bz 1/19/2007 */2068/* ************************************************ */20692070/* Bit masks for TWIx_CONTROL */20712072#define PRESCALE 0x7f /* Prescale Value */2073#define TWI_ENA 0x80 /* TWI Enable */2074#define SCCB 0x200 /* Serial Camera Control Bus */20752076/* Bit maskes for TWIx_CLKDIV */20772078#define CLKLOW 0xff /* Clock Low */2079#define CLKHI 0xff00 /* Clock High */20802081/* Bit maskes for TWIx_SLAVE_CTL */20822083#define SEN 0x1 /* Slave Enable */2084#define STDVAL 0x4 /* Slave Transmit Data Valid */2085#define NAK 0x8 /* Not Acknowledge */2086#define GEN 0x10 /* General Call Enable */20872088/* Bit maskes for TWIx_SLAVE_ADDR */20892090#define SADDR 0x7f /* Slave Mode Address */20912092/* Bit maskes for TWIx_SLAVE_STAT */20932094#define SDIR 0x1 /* Slave Transfer Direction */2095#define GCALL 0x2 /* General Call */20962097/* Bit maskes for TWIx_MASTER_CTL */20982099#define MEN 0x1 /* Master Mode Enable */2100#define MDIR 0x4 /* Master Transfer Direction */2101#define FAST 0x8 /* Fast Mode */2102#define STOP 0x10 /* Issue Stop Condition */2103#define RSTART 0x20 /* Repeat Start */2104#define DCNT 0x3fc0 /* Data Transfer Count */2105#define SDAOVR 0x4000 /* Serial Data Override */2106#define SCLOVR 0x8000 /* Serial Clock Override */21072108/* Bit maskes for TWIx_MASTER_ADDR */21092110#define MADDR 0x7f /* Master Mode Address */21112112/* Bit maskes for TWIx_MASTER_STAT */21132114#define MPROG 0x1 /* Master Transfer in Progress */2115#define LOSTARB 0x2 /* Lost Arbitration */2116#define ANAK 0x4 /* Address Not Acknowledged */2117#define DNAK 0x8 /* Data Not Acknowledged */2118#define BUFRDERR 0x10 /* Buffer Read Error */2119#define BUFWRERR 0x20 /* Buffer Write Error */2120#define SDASEN 0x40 /* Serial Data Sense */2121#define SCLSEN 0x80 /* Serial Clock Sense */2122#define BUSBUSY 0x100 /* Bus Busy */21232124/* Bit maskes for TWIx_FIFO_CTL */21252126#define XMTFLUSH 0x1 /* Transmit Buffer Flush */2127#define RCVFLUSH 0x2 /* Receive Buffer Flush */2128#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */2129#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */21302131/* Bit maskes for TWIx_FIFO_STAT */21322133#define XMTSTAT 0x3 /* Transmit FIFO Status */2134#define RCVSTAT 0xc /* Receive FIFO Status */21352136/* Bit maskes for TWIx_INT_MASK */21372138#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */2139#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */2140#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */2141#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */2142#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */2143#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */2144#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */2145#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */21462147/* Bit maskes for TWIx_INT_STAT */21482149#define SINIT 0x1 /* Slave Transfer Initiated */2150#define SCOMP 0x2 /* Slave Transfer Complete */2151#define SERR 0x4 /* Slave Transfer Error */2152#define SOVF 0x8 /* Slave Overflow */2153#define MCOMP 0x10 /* Master Transfer Complete */2154#define MERR 0x20 /* Master Transfer Error */2155#define XMTSERV 0x40 /* Transmit FIFO Service */2156#define RCVSERV 0x80 /* Receive FIFO Service */21572158/* Bit maskes for TWIx_XMT_DATA8 */21592160#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */21612162/* Bit maskes for TWIx_XMT_DATA16 */21632164#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */21652166/* Bit maskes for TWIx_RCV_DATA8 */21672168#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */21692170/* Bit maskes for TWIx_RCV_DATA16 */21712172#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */21732174/* ******************************************* */2175/* MULTI BIT MACRO ENUMERATIONS */2176/* ******************************************* */21772178/* BCODE bit field options (SYSCFG register) */21792180#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */2181#define BCODE_FULLBOOT 0x0010 /* always perform full boot */2182#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */2183#define BCODE_NOBOOT 0x0030 /* always perform full boot */21842185/* TMODE in TIMERx_CONFIG bit field options */21862187#define PWM_OUT 0x00012188#define WDTH_CAP 0x00022189#define EXT_CLK 0x000321902191/* PINTx Register Bit Definitions */21922193#define PIQ0 0x000000012194#define PIQ1 0x000000022195#define PIQ2 0x000000042196#define PIQ3 0x0000000821972198#define PIQ4 0x000000102199#define PIQ5 0x000000202200#define PIQ6 0x000000402201#define PIQ7 0x0000008022022203#define PIQ8 0x000001002204#define PIQ9 0x000002002205#define PIQ10 0x000004002206#define PIQ11 0x0000080022072208#define PIQ12 0x000010002209#define PIQ13 0x000020002210#define PIQ14 0x000040002211#define PIQ15 0x0000800022122213#define PIQ16 0x000100002214#define PIQ17 0x000200002215#define PIQ18 0x000400002216#define PIQ19 0x0008000022172218#define PIQ20 0x001000002219#define PIQ21 0x002000002220#define PIQ22 0x004000002221#define PIQ23 0x0080000022222223#define PIQ24 0x010000002224#define PIQ25 0x020000002225#define PIQ26 0x040000002226#define PIQ27 0x0800000022272228#define PIQ28 0x100000002229#define PIQ29 0x200000002230#define PIQ30 0x400000002231#define PIQ31 0x8000000022322233/* Port Muxing Bit Fields for PORTx_MUX Registers */22342235#define MUX0 0x000000032236#define MUX0_0 0x000000002237#define MUX0_1 0x000000012238#define MUX0_2 0x000000022239#define MUX0_3 0x0000000322402241#define MUX1 0x0000000C2242#define MUX1_0 0x000000002243#define MUX1_1 0x000000042244#define MUX1_2 0x000000082245#define MUX1_3 0x0000000C22462247#define MUX2 0x000000302248#define MUX2_0 0x000000002249#define MUX2_1 0x000000102250#define MUX2_2 0x000000202251#define MUX2_3 0x0000003022522253#define MUX3 0x000000C02254#define MUX3_0 0x000000002255#define MUX3_1 0x000000402256#define MUX3_2 0x000000802257#define MUX3_3 0x000000C022582259#define MUX4 0x000003002260#define MUX4_0 0x000000002261#define MUX4_1 0x000001002262#define MUX4_2 0x000002002263#define MUX4_3 0x0000030022642265#define MUX5 0x00000C002266#define MUX5_0 0x000000002267#define MUX5_1 0x000004002268#define MUX5_2 0x000008002269#define MUX5_3 0x00000C0022702271#define MUX6 0x000030002272#define MUX6_0 0x000000002273#define MUX6_1 0x000010002274#define MUX6_2 0x000020002275#define MUX6_3 0x0000300022762277#define MUX7 0x0000C0002278#define MUX7_0 0x000000002279#define MUX7_1 0x000040002280#define MUX7_2 0x000080002281#define MUX7_3 0x0000C00022822283#define MUX8 0x000300002284#define MUX8_0 0x000000002285#define MUX8_1 0x000100002286#define MUX8_2 0x000200002287#define MUX8_3 0x0003000022882289#define MUX9 0x000C00002290#define MUX9_0 0x000000002291#define MUX9_1 0x000400002292#define MUX9_2 0x000800002293#define MUX9_3 0x000C000022942295#define MUX10 0x003000002296#define MUX10_0 0x000000002297#define MUX10_1 0x001000002298#define MUX10_2 0x002000002299#define MUX10_3 0x0030000023002301#define MUX11 0x00C000002302#define MUX11_0 0x000000002303#define MUX11_1 0x004000002304#define MUX11_2 0x008000002305#define MUX11_3 0x00C0000023062307#define MUX12 0x030000002308#define MUX12_0 0x000000002309#define MUX12_1 0x010000002310#define MUX12_2 0x020000002311#define MUX12_3 0x0300000023122313#define MUX13 0x0C0000002314#define MUX13_0 0x000000002315#define MUX13_1 0x040000002316#define MUX13_2 0x080000002317#define MUX13_3 0x0C00000023182319#define MUX14 0x300000002320#define MUX14_0 0x000000002321#define MUX14_1 0x100000002322#define MUX14_2 0x200000002323#define MUX14_3 0x3000000023242325#define MUX15 0xC00000002326#define MUX15_0 0x000000002327#define MUX15_1 0x400000002328#define MUX15_2 0x800000002329#define MUX15_3 0xC000000023302331#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \2332((((b15)&3) << 30) | \2333(((b14)&3) << 28) | \2334(((b13)&3) << 26) | \2335(((b12)&3) << 24) | \2336(((b11)&3) << 22) | \2337(((b10)&3) << 20) | \2338(((b9) &3) << 18) | \2339(((b8) &3) << 16) | \2340(((b7) &3) << 14) | \2341(((b6) &3) << 12) | \2342(((b5) &3) << 10) | \2343(((b4) &3) << 8) | \2344(((b3) &3) << 6) | \2345(((b2) &3) << 4) | \2346(((b1) &3) << 2) | \2347(((b0) &3)))23482349/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */23502351#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */2352#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */2353#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */2354#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */2355#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */2356#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */2357#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */2358#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */2359#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */2360#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */2361#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */2362#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */23632364/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */23652366#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */2367#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */2368#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */2369#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */2370#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */2371#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */2372#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */2373#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */23742375#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */2376#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */2377#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */2378#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */2379#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */2380#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */2381#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */2382#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */23832384#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */2385#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */2386#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */2387#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */2388#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */2389#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */2390#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */2391#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */23922393#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */2394#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */2395#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */2396#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */2397#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */2398#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */2399#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */2400#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */24012402#endif /* _DEF_BF54X_H */240324042405