Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
awilliam
GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/blackfin/mach-bf548/include/mach/mem_map.h
15159 views
1
/*
2
* BF548 memory map
3
*
4
* Copyright 2004-2009 Analog Devices Inc.
5
* Licensed under the GPL-2 or later.
6
*/
7
8
#ifndef __BFIN_MACH_MEM_MAP_H__
9
#define __BFIN_MACH_MEM_MAP_H__
10
11
#ifndef __BFIN_MEM_MAP_H__
12
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13
#endif
14
15
/* Async Memory Banks */
16
#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
17
#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
18
#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
19
#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
20
#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
21
#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
22
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
23
#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
24
25
/* Boot ROM Memory */
26
27
#define BOOT_ROM_START 0xEF000000
28
#define BOOT_ROM_LENGTH 0x1000
29
30
/* L1 Instruction ROM */
31
32
#define L1_ROM_START 0xFFA14000
33
#define L1_ROM_LENGTH 0x10000
34
35
/* Level 1 Memory */
36
37
/* Memory Map for ADSP-BF548 processors */
38
#ifdef CONFIG_BFIN_ICACHE
39
#define BFIN_ICACHESIZE (16*1024)
40
#else
41
#define BFIN_ICACHESIZE (0*1024)
42
#endif
43
44
#define L1_CODE_START 0xFFA00000
45
#define L1_DATA_A_START 0xFF800000
46
#define L1_DATA_B_START 0xFF900000
47
48
#define L1_CODE_LENGTH 0xC000
49
50
#ifdef CONFIG_BFIN_DCACHE
51
52
#ifdef CONFIG_BFIN_DCACHE_BANKA
53
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
54
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
55
#define L1_DATA_B_LENGTH 0x8000
56
#define BFIN_DCACHESIZE (16*1024)
57
#define BFIN_DSUPBANKS 1
58
#else
59
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
60
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
61
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
62
#define BFIN_DCACHESIZE (32*1024)
63
#define BFIN_DSUPBANKS 2
64
#endif
65
66
#else
67
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
68
#define L1_DATA_A_LENGTH 0x8000
69
#define L1_DATA_B_LENGTH 0x8000
70
#define BFIN_DCACHESIZE (0*1024)
71
#define BFIN_DSUPBANKS 0
72
#endif /*CONFIG_BFIN_DCACHE*/
73
74
/* Level 2 Memory */
75
#define L2_START 0xFEB00000
76
#if defined(CONFIG_BF542)
77
# define L2_LENGTH 0
78
#elif defined(CONFIG_BF544)
79
# define L2_LENGTH 0x10000
80
#else
81
# define L2_LENGTH 0x20000
82
#endif
83
84
#endif
85
86