Path: blob/master/arch/blackfin/mach-bf561/coreb.c
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/* Load firmware into Core B on a BF5611*2* Copyright 2004-2009 Analog Devices Inc.3* Licensed under the GPL-2 or later.4*/56/* The Core B reset func requires code in the application that is loaded into7* Core B. In order to reset, the application needs to install an interrupt8* handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and9* writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core10* B to stall when Supplemental Interrupt 0 is set, and will reset PC to11* 0xff600000 when COREB_SRAM_INIT is cleared.12*/1314#include <linux/device.h>15#include <linux/fs.h>16#include <linux/kernel.h>17#include <linux/miscdevice.h>18#include <linux/module.h>1920#define CMD_COREB_START _IO('b', 0)21#define CMD_COREB_STOP _IO('b', 1)22#define CMD_COREB_RESET _IO('b', 2)2324static long25coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)26{27int ret = 0;2829switch (cmd) {30case CMD_COREB_START:31bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);32break;33case CMD_COREB_STOP:34bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);35bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);36break;37case CMD_COREB_RESET:38bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);39break;40default:41ret = -EINVAL;42break;43}4445CSYNC();4647return ret;48}4950static const struct file_operations coreb_fops = {51.owner = THIS_MODULE,52.unlocked_ioctl = coreb_ioctl,53.llseek = noop_llseek,54};5556static struct miscdevice coreb_dev = {57.minor = MISC_DYNAMIC_MINOR,58.name = "coreb",59.fops = &coreb_fops,60};6162static int __init bf561_coreb_init(void)63{64return misc_register(&coreb_dev);65}66module_init(bf561_coreb_init);6768static void __exit bf561_coreb_exit(void)69{70misc_deregister(&coreb_dev);71}72module_exit(bf561_coreb_exit);7374MODULE_AUTHOR("Bas Vermeulen <[email protected]>");75MODULE_DESCRIPTION("BF561 Core B Support");76MODULE_LICENSE("GPL");777879