CoCalc -- defBF561.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/blackfin/mach-bf561/include/mach/defBF561.h
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/*
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 * Copyright 2005-2010 Analog Devices Inc.
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 *
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 * Licensed under the ADI BSD license or the GPL-2 (or later)
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 */
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#ifndef _DEF_BF561_H
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#define _DEF_BF561_H
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/*********************************************************************************** */
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/* System MMR Register Map */
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/*********************************************************************************** */
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/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
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#define PLL_CTL                0xFFC00000	/* PLL Control register (16-bit) */
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#define PLL_DIV			        0xFFC00004	/* PLL Divide Register (16-bit) */
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#define VR_CTL			        0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
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#define PLL_STAT               0xFFC0000C	/* PLL Status register (16-bit) */
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#define PLL_LOCKCNT            0xFFC00010	/* PLL Lock Count register (16-bit) */
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#define CHIPID                 0xFFC00014       /* Chip ID Register */
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/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
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#define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
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#define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
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#define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
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#define RESET_SOFTWARE          (SWRST_OCCURRED)
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/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
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#define SWRST                   0xFFC00100	/* Software Reset register */
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#define SYSCR                   0xFFC00104	/* System Reset Configuration register */
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#define SIC_RVECT               0xFFC00108	/* SIC Reset Vector Address Register */
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#define SIC_IMASK0              0xFFC0010C	/* SIC Interrupt Mask register 0 */
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#define SIC_IMASK1              0xFFC00110	/* SIC Interrupt Mask register 1 */
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#define SIC_IAR0                0xFFC00124	/* SIC Interrupt Assignment Register 0 */
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#define SIC_IAR1                0xFFC00128	/* SIC Interrupt Assignment Register 1 */
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#define SIC_IAR2                0xFFC0012C	/* SIC Interrupt Assignment Register 2 */
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#define SIC_IAR3                0xFFC00130	/* SIC Interrupt Assignment Register 3 */
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#define SIC_IAR4                0xFFC00134	/* SIC Interrupt Assignment Register 4 */
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#define SIC_IAR5                0xFFC00138	/* SIC Interrupt Assignment Register 5 */
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#define SIC_IAR6                0xFFC0013C	/* SIC Interrupt Assignment Register 6 */
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#define SIC_IAR7                0xFFC00140	/* SIC Interrupt Assignment Register 7 */
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#define SIC_ISR0                0xFFC00114	/* SIC Interrupt Status register 0 */
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#define SIC_ISR1                0xFFC00118	/* SIC Interrupt Status register 1 */
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#define SIC_IWR0                0xFFC0011C	/* SIC Interrupt Wakeup-Enable register 0 */
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#define SIC_IWR1                0xFFC00120	/* SIC Interrupt Wakeup-Enable register 1 */
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/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
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#define SICB_SWRST              0xFFC01100	/* reserved */
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#define SICB_SYSCR              0xFFC01104	/* reserved */
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#define SICB_RVECT              0xFFC01108	/* SIC Reset Vector Address Register */
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#define SICB_IMASK0             0xFFC0110C	/* SIC Interrupt Mask register 0 */
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#define SICB_IMASK1             0xFFC01110	/* SIC Interrupt Mask register 1 */
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#define SICB_IAR0               0xFFC01124	/* SIC Interrupt Assignment Register 0 */
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#define SICB_IAR1               0xFFC01128	/* SIC Interrupt Assignment Register 1 */
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#define SICB_IAR2               0xFFC0112C	/* SIC Interrupt Assignment Register 2 */
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#define SICB_IAR3               0xFFC01130	/* SIC Interrupt Assignment Register 3 */
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#define SICB_IAR4               0xFFC01134	/* SIC Interrupt Assignment Register 4 */
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#define SICB_IAR5               0xFFC01138	/* SIC Interrupt Assignment Register 5 */
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#define SICB_IAR6               0xFFC0113C	/* SIC Interrupt Assignment Register 6 */
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#define SICB_IAR7               0xFFC01140	/* SIC Interrupt Assignment Register 7 */
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#define SICB_ISR0               0xFFC01114	/* SIC Interrupt Status register 0 */
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#define SICB_ISR1               0xFFC01118	/* SIC Interrupt Status register 1 */
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#define SICB_IWR0               0xFFC0111C	/* SIC Interrupt Wakeup-Enable register 0 */
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#define SICB_IWR1               0xFFC01120	/* SIC Interrupt Wakeup-Enable register 1 */
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/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
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#define WDOGA_CTL 				0xFFC00200	/* Watchdog Control register */
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#define WDOGA_CNT 				0xFFC00204	/* Watchdog Count register */
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#define WDOGA_STAT 				0xFFC00208	/* Watchdog Status register */
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/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
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#define WDOGB_CTL 				0xFFC01200	/* Watchdog Control register */
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#define WDOGB_CNT 				0xFFC01204	/* Watchdog Count register */
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#define WDOGB_STAT 				0xFFC01208	/* Watchdog Status register */
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/* UART Controller (0xFFC00400 - 0xFFC004FF) */
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/*
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 * Because include/linux/serial_reg.h have defined UART_*,
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 * So we define blackfin uart regs to BFIN_UART0_*.
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 */
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#define BFIN_UART_THR			0xFFC00400  /* Transmit Holding register */
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#define BFIN_UART_RBR			0xFFC00400  /* Receive Buffer register */
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#define BFIN_UART_DLL			0xFFC00400  /* Divisor Latch (Low-Byte) */
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#define BFIN_UART_IER			0xFFC00404  /* Interrupt Enable Register */
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#define BFIN_UART_DLH			0xFFC00404  /* Divisor Latch (High-Byte) */
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#define BFIN_UART_IIR			0xFFC00408  /* Interrupt Identification Register */
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#define BFIN_UART_LCR			0xFFC0040C  /* Line Control Register */
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#define BFIN_UART_MCR			0xFFC00410  /* Modem Control Register */
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#define BFIN_UART_LSR			0xFFC00414  /* Line Status Register */
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#define BFIN_UART_MSR			0xFFC00418  /* Modem Status Register */
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#define BFIN_UART_SCR			0xFFC0041C  /* SCR Scratch Register */
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#define BFIN_UART_GCTL			0xFFC00424  /* Global Control Register */
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/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
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#define SPI0_REGBASE          		0xFFC00500
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#define SPI_CTL               		0xFFC00500	/* SPI Control Register */
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#define SPI_FLG               		0xFFC00504	/* SPI Flag register */
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#define SPI_STAT              		0xFFC00508	/* SPI Status register */
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#define SPI_TDBR              		0xFFC0050C	/* SPI Transmit Data Buffer Register */
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#define SPI_RDBR              		0xFFC00510	/* SPI Receive Data Buffer Register */
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#define SPI_BAUD              		0xFFC00514	/* SPI Baud rate Register */
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#define SPI_SHADOW            		0xFFC00518	/* SPI_RDBR Shadow Register */
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/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
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#define TIMER0_CONFIG 				0xFFC00600	/* Timer0 Configuration register */
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#define TIMER0_COUNTER 				0xFFC00604	/* Timer0 Counter register */
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#define TIMER0_PERIOD 				0xFFC00608	/* Timer0 Period register */
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#define TIMER0_WIDTH 				0xFFC0060C	/* Timer0 Width register */
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#define TIMER1_CONFIG 				0xFFC00610	/* Timer1 Configuration register */
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#define TIMER1_COUNTER 				0xFFC00614	/* Timer1 Counter register */
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#define TIMER1_PERIOD 				0xFFC00618	/* Timer1 Period register */
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#define TIMER1_WIDTH 				0xFFC0061C	/* Timer1 Width register */
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#define TIMER2_CONFIG 				0xFFC00620	/* Timer2 Configuration register */
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#define TIMER2_COUNTER 				0xFFC00624	/* Timer2 Counter register */
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#define TIMER2_PERIOD 				0xFFC00628	/* Timer2 Period register */
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#define TIMER2_WIDTH 				0xFFC0062C	/* Timer2 Width register */
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#define TIMER3_CONFIG 				0xFFC00630	/* Timer3 Configuration register */
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#define TIMER3_COUNTER 				0xFFC00634	/* Timer3 Counter register */
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#define TIMER3_PERIOD 				0xFFC00638	/* Timer3 Period register */
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#define TIMER3_WIDTH 				0xFFC0063C	/* Timer3 Width register */
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#define TIMER4_CONFIG 				0xFFC00640	/* Timer4 Configuration register */
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#define TIMER4_COUNTER 				0xFFC00644	/* Timer4 Counter register */
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#define TIMER4_PERIOD 				0xFFC00648	/* Timer4 Period register */
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#define TIMER4_WIDTH 				0xFFC0064C	/* Timer4 Width register */
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#define TIMER5_CONFIG 				0xFFC00650	/* Timer5 Configuration register */
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#define TIMER5_COUNTER 				0xFFC00654	/* Timer5 Counter register */
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#define TIMER5_PERIOD 				0xFFC00658	/* Timer5 Period register */
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#define TIMER5_WIDTH 				0xFFC0065C	/* Timer5 Width register */
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#define TIMER6_CONFIG 				0xFFC00660	/* Timer6 Configuration register */
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#define TIMER6_COUNTER 				0xFFC00664	/* Timer6 Counter register */
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#define TIMER6_PERIOD 				0xFFC00668	/* Timer6 Period register */
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#define TIMER6_WIDTH 				0xFFC0066C	/* Timer6 Width register */
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#define TIMER7_CONFIG 				0xFFC00670	/* Timer7 Configuration register */
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#define TIMER7_COUNTER 				0xFFC00674	/* Timer7 Counter register */
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#define TIMER7_PERIOD 				0xFFC00678	/* Timer7 Period register */
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#define TIMER7_WIDTH 				0xFFC0067C	/* Timer7 Width register */
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#define TMRS8_ENABLE 				0xFFC00680	/* Timer Enable Register */
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#define TMRS8_DISABLE 				0xFFC00684	/* Timer Disable register */
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#define TMRS8_STATUS 				0xFFC00688	/* Timer Status register */
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/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
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#define TIMER8_CONFIG 				0xFFC01600	/* Timer8 Configuration register */
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#define TIMER8_COUNTER 				0xFFC01604	/* Timer8 Counter register */
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#define TIMER8_PERIOD 				0xFFC01608	/* Timer8 Period register */
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#define TIMER8_WIDTH 				0xFFC0160C	/* Timer8 Width register */
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#define TIMER9_CONFIG 				0xFFC01610	/* Timer9 Configuration register */
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#define TIMER9_COUNTER 				0xFFC01614	/* Timer9 Counter register */
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#define TIMER9_PERIOD 				0xFFC01618	/* Timer9 Period register */
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#define TIMER9_WIDTH 				0xFFC0161C	/* Timer9 Width register */
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#define TIMER10_CONFIG 				0xFFC01620	/* Timer10 Configuration register */
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#define TIMER10_COUNTER 			0xFFC01624	/* Timer10 Counter register */
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#define TIMER10_PERIOD 				0xFFC01628	/* Timer10 Period register */
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#define TIMER10_WIDTH 				0xFFC0162C	/* Timer10 Width register */
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#define TIMER11_CONFIG 				0xFFC01630	/* Timer11 Configuration register */
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#define TIMER11_COUNTER 			0xFFC01634	/* Timer11 Counter register */
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#define TIMER11_PERIOD 				0xFFC01638	/* Timer11 Period register */
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#define TIMER11_WIDTH 				0xFFC0163C	/* Timer11 Width register */
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#define TMRS4_ENABLE 				0xFFC01640	/* Timer Enable Register */
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#define TMRS4_DISABLE 				0xFFC01644	/* Timer Disable register */
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#define TMRS4_STATUS 				0xFFC01648	/* Timer Status register */
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/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
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#define FIO0_FLAG_D 				0xFFC00700	/* Flag Data register */
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#define FIO0_FLAG_C 				0xFFC00704	/* Flag Clear register */
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#define FIO0_FLAG_S 				0xFFC00708	/* Flag Set register */
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#define FIO0_FLAG_T 				0xFFC0070C	/* Flag Toggle register */
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#define FIO0_MASKA_D 				0xFFC00710	/* Flag Mask Interrupt A Data register */
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#define FIO0_MASKA_C 				0xFFC00714	/* Flag Mask Interrupt A Clear register */
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#define FIO0_MASKA_S 				0xFFC00718	/* Flag Mask Interrupt A Set register */
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#define FIO0_MASKA_T 				0xFFC0071C	/* Flag Mask Interrupt A Toggle register */
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#define FIO0_MASKB_D 				0xFFC00720	/* Flag Mask Interrupt B Data register */
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#define FIO0_MASKB_C 				0xFFC00724	/* Flag Mask Interrupt B Clear register */
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#define FIO0_MASKB_S 				0xFFC00728	/* Flag Mask Interrupt B Set register */
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#define FIO0_MASKB_T 				0xFFC0072C	/* Flag Mask Interrupt B Toggle register */
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#define FIO0_DIR 					0xFFC00730	/* Flag Direction register */
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#define FIO0_POLAR 					0xFFC00734	/* Flag Polarity register */
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#define FIO0_EDGE 					0xFFC00738	/* Flag Interrupt Sensitivity register */
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#define FIO0_BOTH 					0xFFC0073C	/* Flag Set on Both Edges register */
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#define FIO0_INEN 					0xFFC00740	/* Flag Input Enable register */
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/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
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#define FIO1_FLAG_D 				0xFFC01500	/* Flag Data register (mask used to directly */
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#define FIO1_FLAG_C 				0xFFC01504	/* Flag Clear register */
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#define FIO1_FLAG_S 				0xFFC01508	/* Flag Set register */
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#define FIO1_FLAG_T 				0xFFC0150C	/* Flag Toggle register (mask used to */
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#define FIO1_MASKA_D 				0xFFC01510	/* Flag Mask Interrupt A Data register */
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#define FIO1_MASKA_C 				0xFFC01514	/* Flag Mask Interrupt A Clear register */
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#define FIO1_MASKA_S 				0xFFC01518	/* Flag Mask Interrupt A Set register */
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#define FIO1_MASKA_T 				0xFFC0151C	/* Flag Mask Interrupt A Toggle register */
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#define FIO1_MASKB_D 				0xFFC01520	/* Flag Mask Interrupt B Data register */
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#define FIO1_MASKB_C 				0xFFC01524	/* Flag Mask Interrupt B Clear register */
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#define FIO1_MASKB_S 				0xFFC01528	/* Flag Mask Interrupt B Set register */
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#define FIO1_MASKB_T 				0xFFC0152C	/* Flag Mask Interrupt B Toggle register */
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#define FIO1_DIR 					0xFFC01530	/* Flag Direction register */
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#define FIO1_POLAR 					0xFFC01534	/* Flag Polarity register */
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#define FIO1_EDGE 					0xFFC01538	/* Flag Interrupt Sensitivity register */
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#define FIO1_BOTH 					0xFFC0153C	/* Flag Set on Both Edges register */
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#define FIO1_INEN 					0xFFC01540	/* Flag Input Enable register */
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/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
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#define FIO2_FLAG_D 				0xFFC01700	/* Flag Data register (mask used to directly */
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#define FIO2_FLAG_C 				0xFFC01704	/* Flag Clear register */
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#define FIO2_FLAG_S 				0xFFC01708	/* Flag Set register */
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#define FIO2_FLAG_T 				0xFFC0170C	/* Flag Toggle register (mask used to */
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#define FIO2_MASKA_D 				0xFFC01710	/* Flag Mask Interrupt A Data register */
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#define FIO2_MASKA_C 				0xFFC01714	/* Flag Mask Interrupt A Clear register */
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#define FIO2_MASKA_S 				0xFFC01718	/* Flag Mask Interrupt A Set register */
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#define FIO2_MASKA_T 				0xFFC0171C	/* Flag Mask Interrupt A Toggle register */
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#define FIO2_MASKB_D 				0xFFC01720	/* Flag Mask Interrupt B Data register */
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#define FIO2_MASKB_C 				0xFFC01724	/* Flag Mask Interrupt B Clear register */
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#define FIO2_MASKB_S 				0xFFC01728	/* Flag Mask Interrupt B Set register */
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#define FIO2_MASKB_T 				0xFFC0172C	/* Flag Mask Interrupt B Toggle register */
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#define FIO2_DIR 					0xFFC01730	/* Flag Direction register */
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#define FIO2_POLAR 					0xFFC01734	/* Flag Polarity register */
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#define FIO2_EDGE 					0xFFC01738	/* Flag Interrupt Sensitivity register */
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#define FIO2_BOTH 					0xFFC0173C	/* Flag Set on Both Edges register */
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#define FIO2_INEN 					0xFFC01740	/* Flag Input Enable register */
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/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
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#define SPORT0_TCR1     	 	0xFFC00800	/* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_TCR2      	 	0xFFC00804	/* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_TCLKDIV        		0xFFC00808	/* SPORT0 Transmit Clock Divider */
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#define SPORT0_TFSDIV          		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider */
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#define SPORT0_TX	             	0xFFC00810	/* SPORT0 TX Data Register */
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#define SPORT0_RX	            	0xFFC00818	/* SPORT0 RX Data Register */
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#define SPORT0_RCR1      	 		0xFFC00820	/* SPORT0 Transmit Configuration 1 Register */
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#define SPORT0_RCR2      	 		0xFFC00824	/* SPORT0 Transmit Configuration 2 Register */
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#define SPORT0_RCLKDIV        		0xFFC00828	/* SPORT0 Receive Clock Divider */
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#define SPORT0_RFSDIV          		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider */
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#define SPORT0_STAT            		0xFFC00830	/* SPORT0 Status Register */
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#define SPORT0_CHNL            		0xFFC00834	/* SPORT0 Current Channel Register */
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#define SPORT0_MCMC1           		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1 */
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#define SPORT0_MCMC2           		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2 */
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#define SPORT0_MTCS0           		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0 */
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#define SPORT0_MTCS1           		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1 */
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#define SPORT0_MTCS2           		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2 */
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#define SPORT0_MTCS3           		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3 */
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#define SPORT0_MRCS0           		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0 */
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#define SPORT0_MRCS1           		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1 */
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#define SPORT0_MRCS2           		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2 */
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#define SPORT0_MRCS3           		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3 */
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/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
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#define SPORT1_TCR1     	 		0xFFC00900	/* SPORT1 Transmit Configuration 1 Register */
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#define SPORT1_TCR2      	 		0xFFC00904	/* SPORT1 Transmit Configuration 2 Register */
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#define SPORT1_TCLKDIV        		0xFFC00908	/* SPORT1 Transmit Clock Divider */
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#define SPORT1_TFSDIV          		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider */
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#define SPORT1_TX	             	0xFFC00910	/* SPORT1 TX Data Register */
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#define SPORT1_RX	            	0xFFC00918	/* SPORT1 RX Data Register */
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#define SPORT1_RCR1      	 		0xFFC00920	/* SPORT1 Transmit Configuration 1 Register */
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#define SPORT1_RCR2      	 		0xFFC00924	/* SPORT1 Transmit Configuration 2 Register */
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#define SPORT1_RCLKDIV        		0xFFC00928	/* SPORT1 Receive Clock Divider */
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#define SPORT1_RFSDIV          		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider */
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#define SPORT1_STAT            		0xFFC00930	/* SPORT1 Status Register */
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#define SPORT1_CHNL            		0xFFC00934	/* SPORT1 Current Channel Register */
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#define SPORT1_MCMC1           		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1 */
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#define SPORT1_MCMC2           		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2 */
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#define SPORT1_MTCS0           		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0 */
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#define SPORT1_MTCS1           		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1 */
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#define SPORT1_MTCS2           		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2 */
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#define SPORT1_MTCS3           		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3 */
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#define SPORT1_MRCS0           		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0 */
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#define SPORT1_MRCS1           		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1 */
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#define SPORT1_MRCS2           		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2 */
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#define SPORT1_MRCS3           		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3 */
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/* Asynchronous Memory Controller - External Bus Interface Unit  */
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#define EBIU_AMGCTL					0xFFC00A00	/* Asynchronous Memory Global Control Register */
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#define EBIU_AMBCTL0				0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */
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#define EBIU_AMBCTL1				0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */
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/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
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#define EBIU_SDGCTL					0xFFC00A10	/* SDRAM Global Control Register */
288
#define EBIU_SDBCTL					0xFFC00A14	/* SDRAM Bank Control Register */
289
#define EBIU_SDRRC 					0xFFC00A18	/* SDRAM Refresh Rate Control Register */
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#define EBIU_SDSTAT					0xFFC00A1C	/* SDRAM Status Register */
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/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
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#define PPI0_CONTROL 				0xFFC01000	/* PPI0 Control register */
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#define PPI0_STATUS 				0xFFC01004	/* PPI0 Status register */
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#define PPI0_COUNT 					0xFFC01008	/* PPI0 Transfer Count register */
296
#define PPI0_DELAY 					0xFFC0100C	/* PPI0 Delay Count register */
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#define PPI0_FRAME 					0xFFC01010	/* PPI0 Frame Length register */
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/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
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#define PPI1_CONTROL 				0xFFC01300	/* PPI1 Control register */
301
#define PPI1_STATUS 				0xFFC01304	/* PPI1 Status register */
302
#define PPI1_COUNT 					0xFFC01308	/* PPI1 Transfer Count register */
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#define PPI1_DELAY 					0xFFC0130C	/* PPI1 Delay Count register */
304
#define PPI1_FRAME 					0xFFC01310	/* PPI1 Frame Length register */
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/*DMA traffic control registers */
307
#define	DMAC0_TC_PER  0xFFC00B0C	/* Traffic control periods */
308
#define	DMAC0_TC_CNT  0xFFC00B10	/* Traffic control current counts        */
309
#define	DMAC1_TC_PER  0xFFC01B0C	/* Traffic control periods */
310
#define	DMAC1_TC_CNT  0xFFC01B10	/* Traffic control current counts */
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312
/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
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#define DMA1_0_CONFIG 0xFFC01C08	/* DMA1 Channel 0 Configuration register */
314
#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00	/* DMA1 Channel 0 Next Descripter Ptr Reg */
315
#define DMA1_0_START_ADDR 0xFFC01C04	/* DMA1 Channel 0 Start Address */
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#define DMA1_0_X_COUNT 0xFFC01C10	/* DMA1 Channel 0 Inner Loop Count */
317
#define DMA1_0_Y_COUNT 0xFFC01C18	/* DMA1 Channel 0 Outer Loop Count */
318
#define DMA1_0_X_MODIFY 0xFFC01C14	/* DMA1 Channel 0 Inner Loop Addr Increment */
319
#define DMA1_0_Y_MODIFY 0xFFC01C1C	/* DMA1 Channel 0 Outer Loop Addr Increment */
320
#define DMA1_0_CURR_DESC_PTR 0xFFC01C20	/* DMA1 Channel 0 Current Descriptor Pointer */
321
#define DMA1_0_CURR_ADDR 0xFFC01C24	/* DMA1 Channel 0 Current Address Pointer */
322
#define DMA1_0_CURR_X_COUNT 0xFFC01C30	/* DMA1 Channel 0 Current Inner Loop Count */
323
#define DMA1_0_CURR_Y_COUNT 0xFFC01C38	/* DMA1 Channel 0 Current Outer Loop Count */
324
#define DMA1_0_IRQ_STATUS 0xFFC01C28	/* DMA1 Channel 0 Interrupt/Status Register */
325
#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C	/* DMA1 Channel 0 Peripheral Map Register */
326

327
#define DMA1_1_CONFIG 0xFFC01C48	/* DMA1 Channel 1 Configuration register */
328
#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40	/* DMA1 Channel 1 Next Descripter Ptr Reg */
329
#define DMA1_1_START_ADDR 0xFFC01C44	/* DMA1 Channel 1 Start Address */
330
#define DMA1_1_X_COUNT 0xFFC01C50	/* DMA1 Channel 1 Inner Loop Count */
331
#define DMA1_1_Y_COUNT 0xFFC01C58	/* DMA1 Channel 1 Outer Loop Count */
332
#define DMA1_1_X_MODIFY 0xFFC01C54	/* DMA1 Channel 1 Inner Loop Addr Increment */
333
#define DMA1_1_Y_MODIFY 0xFFC01C5C	/* DMA1 Channel 1 Outer Loop Addr Increment */
334
#define DMA1_1_CURR_DESC_PTR 0xFFC01C60	/* DMA1 Channel 1 Current Descriptor Pointer */
335
#define DMA1_1_CURR_ADDR 0xFFC01C64	/* DMA1 Channel 1 Current Address Pointer */
336
#define DMA1_1_CURR_X_COUNT 0xFFC01C70	/* DMA1 Channel 1 Current Inner Loop Count */
337
#define DMA1_1_CURR_Y_COUNT 0xFFC01C78	/* DMA1 Channel 1 Current Outer Loop Count */
338
#define DMA1_1_IRQ_STATUS 0xFFC01C68	/* DMA1 Channel 1 Interrupt/Status Register */
339
#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C	/* DMA1 Channel 1 Peripheral Map Register */
340

341
#define DMA1_2_CONFIG 0xFFC01C88	/* DMA1 Channel 2 Configuration register */
342
#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80	/* DMA1 Channel 2 Next Descripter Ptr Reg */
343
#define DMA1_2_START_ADDR 0xFFC01C84	/* DMA1 Channel 2 Start Address */
344
#define DMA1_2_X_COUNT 0xFFC01C90	/* DMA1 Channel 2 Inner Loop Count */
345
#define DMA1_2_Y_COUNT 0xFFC01C98	/* DMA1 Channel 2 Outer Loop Count */
346
#define DMA1_2_X_MODIFY 0xFFC01C94	/* DMA1 Channel 2 Inner Loop Addr Increment */
347
#define DMA1_2_Y_MODIFY 0xFFC01C9C	/* DMA1 Channel 2 Outer Loop Addr Increment */
348
#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0	/* DMA1 Channel 2 Current Descriptor Pointer */
349
#define DMA1_2_CURR_ADDR 0xFFC01CA4	/* DMA1 Channel 2 Current Address Pointer */
350
#define DMA1_2_CURR_X_COUNT 0xFFC01CB0	/* DMA1 Channel 2 Current Inner Loop Count */
351
#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8	/* DMA1 Channel 2 Current Outer Loop Count */
352
#define DMA1_2_IRQ_STATUS 0xFFC01CA8	/* DMA1 Channel 2 Interrupt/Status Register */
353
#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC	/* DMA1 Channel 2 Peripheral Map Register */
354

355
#define DMA1_3_CONFIG 0xFFC01CC8	/* DMA1 Channel 3 Configuration register */
356
#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0	/* DMA1 Channel 3 Next Descripter Ptr Reg */
357
#define DMA1_3_START_ADDR 0xFFC01CC4	/* DMA1 Channel 3 Start Address */
358
#define DMA1_3_X_COUNT 0xFFC01CD0	/* DMA1 Channel 3 Inner Loop Count */
359
#define DMA1_3_Y_COUNT 0xFFC01CD8	/* DMA1 Channel 3 Outer Loop Count */
360
#define DMA1_3_X_MODIFY 0xFFC01CD4	/* DMA1 Channel 3 Inner Loop Addr Increment */
361
#define DMA1_3_Y_MODIFY 0xFFC01CDC	/* DMA1 Channel 3 Outer Loop Addr Increment */
362
#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0	/* DMA1 Channel 3 Current Descriptor Pointer */
363
#define DMA1_3_CURR_ADDR 0xFFC01CE4	/* DMA1 Channel 3 Current Address Pointer */
364
#define DMA1_3_CURR_X_COUNT 0xFFC01CF0	/* DMA1 Channel 3 Current Inner Loop Count */
365
#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8	/* DMA1 Channel 3 Current Outer Loop Count */
366
#define DMA1_3_IRQ_STATUS 0xFFC01CE8	/* DMA1 Channel 3 Interrupt/Status Register */
367
#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC	/* DMA1 Channel 3 Peripheral Map Register */
368

369
#define DMA1_4_CONFIG 0xFFC01D08	/* DMA1 Channel 4 Configuration register */
370
#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00	/* DMA1 Channel 4 Next Descripter Ptr Reg */
371
#define DMA1_4_START_ADDR 0xFFC01D04	/* DMA1 Channel 4 Start Address */
372
#define DMA1_4_X_COUNT 0xFFC01D10	/* DMA1 Channel 4 Inner Loop Count */
373
#define DMA1_4_Y_COUNT 0xFFC01D18	/* DMA1 Channel 4 Outer Loop Count */
374
#define DMA1_4_X_MODIFY 0xFFC01D14	/* DMA1 Channel 4 Inner Loop Addr Increment */
375
#define DMA1_4_Y_MODIFY 0xFFC01D1C	/* DMA1 Channel 4 Outer Loop Addr Increment */
376
#define DMA1_4_CURR_DESC_PTR 0xFFC01D20	/* DMA1 Channel 4 Current Descriptor Pointer */
377
#define DMA1_4_CURR_ADDR 0xFFC01D24	/* DMA1 Channel 4 Current Address Pointer */
378
#define DMA1_4_CURR_X_COUNT 0xFFC01D30	/* DMA1 Channel 4 Current Inner Loop Count */
379
#define DMA1_4_CURR_Y_COUNT 0xFFC01D38	/* DMA1 Channel 4 Current Outer Loop Count */
380
#define DMA1_4_IRQ_STATUS 0xFFC01D28	/* DMA1 Channel 4 Interrupt/Status Register */
381
#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C	/* DMA1 Channel 4 Peripheral Map Register */
382

383
#define DMA1_5_CONFIG 0xFFC01D48	/* DMA1 Channel 5 Configuration register */
384
#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40	/* DMA1 Channel 5 Next Descripter Ptr Reg */
385
#define DMA1_5_START_ADDR 0xFFC01D44	/* DMA1 Channel 5 Start Address */
386
#define DMA1_5_X_COUNT 0xFFC01D50	/* DMA1 Channel 5 Inner Loop Count */
387
#define DMA1_5_Y_COUNT 0xFFC01D58	/* DMA1 Channel 5 Outer Loop Count */
388
#define DMA1_5_X_MODIFY 0xFFC01D54	/* DMA1 Channel 5 Inner Loop Addr Increment */
389
#define DMA1_5_Y_MODIFY 0xFFC01D5C	/* DMA1 Channel 5 Outer Loop Addr Increment */
390
#define DMA1_5_CURR_DESC_PTR 0xFFC01D60	/* DMA1 Channel 5 Current Descriptor Pointer */
391
#define DMA1_5_CURR_ADDR 0xFFC01D64	/* DMA1 Channel 5 Current Address Pointer */
392
#define DMA1_5_CURR_X_COUNT 0xFFC01D70	/* DMA1 Channel 5 Current Inner Loop Count */
393
#define DMA1_5_CURR_Y_COUNT 0xFFC01D78	/* DMA1 Channel 5 Current Outer Loop Count */
394
#define DMA1_5_IRQ_STATUS 0xFFC01D68	/* DMA1 Channel 5 Interrupt/Status Register */
395
#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C	/* DMA1 Channel 5 Peripheral Map Register */
396

397
#define DMA1_6_CONFIG 0xFFC01D88	/* DMA1 Channel 6 Configuration register */
398
#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80	/* DMA1 Channel 6 Next Descripter Ptr Reg */
399
#define DMA1_6_START_ADDR 0xFFC01D84	/* DMA1 Channel 6 Start Address */
400
#define DMA1_6_X_COUNT 0xFFC01D90	/* DMA1 Channel 6 Inner Loop Count */
401
#define DMA1_6_Y_COUNT 0xFFC01D98	/* DMA1 Channel 6 Outer Loop Count */
402
#define DMA1_6_X_MODIFY 0xFFC01D94	/* DMA1 Channel 6 Inner Loop Addr Increment */
403
#define DMA1_6_Y_MODIFY 0xFFC01D9C	/* DMA1 Channel 6 Outer Loop Addr Increment */
404
#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0	/* DMA1 Channel 6 Current Descriptor Pointer */
405
#define DMA1_6_CURR_ADDR 0xFFC01DA4	/* DMA1 Channel 6 Current Address Pointer */
406
#define DMA1_6_CURR_X_COUNT 0xFFC01DB0	/* DMA1 Channel 6 Current Inner Loop Count */
407
#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8	/* DMA1 Channel 6 Current Outer Loop Count */
408
#define DMA1_6_IRQ_STATUS 0xFFC01DA8	/* DMA1 Channel 6 Interrupt/Status Register */
409
#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC	/* DMA1 Channel 6 Peripheral Map Register */
410

411
#define DMA1_7_CONFIG 0xFFC01DC8	/* DMA1 Channel 7 Configuration register */
412
#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0	/* DMA1 Channel 7 Next Descripter Ptr Reg */
413
#define DMA1_7_START_ADDR 0xFFC01DC4	/* DMA1 Channel 7 Start Address */
414
#define DMA1_7_X_COUNT 0xFFC01DD0	/* DMA1 Channel 7 Inner Loop Count */
415
#define DMA1_7_Y_COUNT 0xFFC01DD8	/* DMA1 Channel 7 Outer Loop Count */
416
#define DMA1_7_X_MODIFY 0xFFC01DD4	/* DMA1 Channel 7 Inner Loop Addr Increment */
417
#define DMA1_7_Y_MODIFY 0xFFC01DDC	/* DMA1 Channel 7 Outer Loop Addr Increment */
418
#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0	/* DMA1 Channel 7 Current Descriptor Pointer */
419
#define DMA1_7_CURR_ADDR 0xFFC01DE4	/* DMA1 Channel 7 Current Address Pointer */
420
#define DMA1_7_CURR_X_COUNT 0xFFC01DF0	/* DMA1 Channel 7 Current Inner Loop Count */
421
#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8	/* DMA1 Channel 7 Current Outer Loop Count */
422
#define DMA1_7_IRQ_STATUS 0xFFC01DE8	/* DMA1 Channel 7 Interrupt/Status Register */
423
#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC	/* DMA1 Channel 7 Peripheral Map Register */
424

425
#define DMA1_8_CONFIG 0xFFC01E08	/* DMA1 Channel 8 Configuration register */
426
#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00	/* DMA1 Channel 8 Next Descripter Ptr Reg */
427
#define DMA1_8_START_ADDR 0xFFC01E04	/* DMA1 Channel 8 Start Address */
428
#define DMA1_8_X_COUNT 0xFFC01E10	/* DMA1 Channel 8 Inner Loop Count */
429
#define DMA1_8_Y_COUNT 0xFFC01E18	/* DMA1 Channel 8 Outer Loop Count */
430
#define DMA1_8_X_MODIFY 0xFFC01E14	/* DMA1 Channel 8 Inner Loop Addr Increment */
431
#define DMA1_8_Y_MODIFY 0xFFC01E1C	/* DMA1 Channel 8 Outer Loop Addr Increment */
432
#define DMA1_8_CURR_DESC_PTR 0xFFC01E20	/* DMA1 Channel 8 Current Descriptor Pointer */
433
#define DMA1_8_CURR_ADDR 0xFFC01E24	/* DMA1 Channel 8 Current Address Pointer */
434
#define DMA1_8_CURR_X_COUNT 0xFFC01E30	/* DMA1 Channel 8 Current Inner Loop Count */
435
#define DMA1_8_CURR_Y_COUNT 0xFFC01E38	/* DMA1 Channel 8 Current Outer Loop Count */
436
#define DMA1_8_IRQ_STATUS 0xFFC01E28	/* DMA1 Channel 8 Interrupt/Status Register */
437
#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C	/* DMA1 Channel 8 Peripheral Map Register */
438

439
#define DMA1_9_CONFIG 0xFFC01E48	/* DMA1 Channel 9 Configuration register */
440
#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40	/* DMA1 Channel 9 Next Descripter Ptr Reg */
441
#define DMA1_9_START_ADDR 0xFFC01E44	/* DMA1 Channel 9 Start Address */
442
#define DMA1_9_X_COUNT 0xFFC01E50	/* DMA1 Channel 9 Inner Loop Count */
443
#define DMA1_9_Y_COUNT 0xFFC01E58	/* DMA1 Channel 9 Outer Loop Count */
444
#define DMA1_9_X_MODIFY 0xFFC01E54	/* DMA1 Channel 9 Inner Loop Addr Increment */
445
#define DMA1_9_Y_MODIFY 0xFFC01E5C	/* DMA1 Channel 9 Outer Loop Addr Increment */
446
#define DMA1_9_CURR_DESC_PTR 0xFFC01E60	/* DMA1 Channel 9 Current Descriptor Pointer */
447
#define DMA1_9_CURR_ADDR 0xFFC01E64	/* DMA1 Channel 9 Current Address Pointer */
448
#define DMA1_9_CURR_X_COUNT 0xFFC01E70	/* DMA1 Channel 9 Current Inner Loop Count */
449
#define DMA1_9_CURR_Y_COUNT 0xFFC01E78	/* DMA1 Channel 9 Current Outer Loop Count */
450
#define DMA1_9_IRQ_STATUS 0xFFC01E68	/* DMA1 Channel 9 Interrupt/Status Register */
451
#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C	/* DMA1 Channel 9 Peripheral Map Register */
452

453
#define DMA1_10_CONFIG 0xFFC01E88	/* DMA1 Channel 10 Configuration register */
454
#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80	/* DMA1 Channel 10 Next Descripter Ptr Reg */
455
#define DMA1_10_START_ADDR 0xFFC01E84	/* DMA1 Channel 10 Start Address */
456
#define DMA1_10_X_COUNT 0xFFC01E90	/* DMA1 Channel 10 Inner Loop Count */
457
#define DMA1_10_Y_COUNT 0xFFC01E98	/* DMA1 Channel 10 Outer Loop Count */
458
#define DMA1_10_X_MODIFY 0xFFC01E94	/* DMA1 Channel 10 Inner Loop Addr Increment */
459
#define DMA1_10_Y_MODIFY 0xFFC01E9C	/* DMA1 Channel 10 Outer Loop Addr Increment */
460
#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0	/* DMA1 Channel 10 Current Descriptor Pointer */
461
#define DMA1_10_CURR_ADDR 0xFFC01EA4	/* DMA1 Channel 10 Current Address Pointer */
462
#define DMA1_10_CURR_X_COUNT 0xFFC01EB0	/* DMA1 Channel 10 Current Inner Loop Count */
463
#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8	/* DMA1 Channel 10 Current Outer Loop Count */
464
#define DMA1_10_IRQ_STATUS 0xFFC01EA8	/* DMA1 Channel 10 Interrupt/Status Register */
465
#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC	/* DMA1 Channel 10 Peripheral Map Register */
466

467
#define DMA1_11_CONFIG 0xFFC01EC8	/* DMA1 Channel 11 Configuration register */
468
#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0	/* DMA1 Channel 11 Next Descripter Ptr Reg */
469
#define DMA1_11_START_ADDR 0xFFC01EC4	/* DMA1 Channel 11 Start Address */
470
#define DMA1_11_X_COUNT 0xFFC01ED0	/* DMA1 Channel 11 Inner Loop Count */
471
#define DMA1_11_Y_COUNT 0xFFC01ED8	/* DMA1 Channel 11 Outer Loop Count */
472
#define DMA1_11_X_MODIFY 0xFFC01ED4	/* DMA1 Channel 11 Inner Loop Addr Increment */
473
#define DMA1_11_Y_MODIFY 0xFFC01EDC	/* DMA1 Channel 11 Outer Loop Addr Increment */
474
#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0	/* DMA1 Channel 11 Current Descriptor Pointer */
475
#define DMA1_11_CURR_ADDR 0xFFC01EE4	/* DMA1 Channel 11 Current Address Pointer */
476
#define DMA1_11_CURR_X_COUNT 0xFFC01EF0	/* DMA1 Channel 11 Current Inner Loop Count */
477
#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8	/* DMA1 Channel 11 Current Outer Loop Count */
478
#define DMA1_11_IRQ_STATUS 0xFFC01EE8	/* DMA1 Channel 11 Interrupt/Status Register */
479
#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC	/* DMA1 Channel 11 Peripheral Map Register */
480

481
/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
482
#define MDMA_D2_CONFIG 0xFFC01F08	/*MemDMA1 Stream 0 Destination Configuration */
483
#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00	/*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
484
#define MDMA_D2_START_ADDR 0xFFC01F04	/*MemDMA1 Stream 0 Destination Start Address */
485
#define MDMA_D2_X_COUNT 0xFFC01F10	/*MemDMA1 Stream 0 Destination Inner-Loop Count */
486
#define MDMA_D2_Y_COUNT 0xFFC01F18	/*MemDMA1 Stream 0 Destination Outer-Loop Count */
487
#define MDMA_D2_X_MODIFY 0xFFC01F14	/*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
488
#define MDMA_D2_Y_MODIFY 0xFFC01F1C	/*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
489
#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20	/*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
490
#define MDMA_D2_CURR_ADDR 0xFFC01F24	/*MemDMA1 Stream 0 Destination Current Address */
491
#define MDMA_D2_CURR_X_COUNT 0xFFC01F30	/*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
492
#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38	/*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
493
#define MDMA_D2_IRQ_STATUS 0xFFC01F28	/*MemDMA1 Stream 0 Destination Interrupt/Status */
494
#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C	/*MemDMA1 Stream 0 Destination Peripheral Map */
495

496
#define MDMA_S2_CONFIG 0xFFC01F48	/*MemDMA1 Stream 0 Source Configuration */
497
#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40	/*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
498
#define MDMA_S2_START_ADDR 0xFFC01F44	/*MemDMA1 Stream 0 Source Start Address */
499
#define MDMA_S2_X_COUNT 0xFFC01F50	/*MemDMA1 Stream 0 Source Inner-Loop Count */
500
#define MDMA_S2_Y_COUNT 0xFFC01F58	/*MemDMA1 Stream 0 Source Outer-Loop Count */
501
#define MDMA_S2_X_MODIFY 0xFFC01F54	/*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
502
#define MDMA_S2_Y_MODIFY 0xFFC01F5C	/*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
503
#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60	/*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
504
#define MDMA_S2_CURR_ADDR 0xFFC01F64	/*MemDMA1 Stream 0 Source Current Address */
505
#define MDMA_S2_CURR_X_COUNT 0xFFC01F70	/*MemDMA1 Stream 0 Source Current Inner-Loop Count */
506
#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78	/*MemDMA1 Stream 0 Source Current Outer-Loop Count */
507
#define MDMA_S2_IRQ_STATUS 0xFFC01F68	/*MemDMA1 Stream 0 Source Interrupt/Status */
508
#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C	/*MemDMA1 Stream 0 Source Peripheral Map */
509

510
#define MDMA_D3_CONFIG 0xFFC01F88	/*MemDMA1 Stream 1 Destination Configuration */
511
#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80	/*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
512
#define MDMA_D3_START_ADDR 0xFFC01F84	/*MemDMA1 Stream 1 Destination Start Address */
513
#define MDMA_D3_X_COUNT 0xFFC01F90	/*MemDMA1 Stream 1 Destination Inner-Loop Count */
514
#define MDMA_D3_Y_COUNT 0xFFC01F98	/*MemDMA1 Stream 1 Destination Outer-Loop Count */
515
#define MDMA_D3_X_MODIFY 0xFFC01F94	/*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
516
#define MDMA_D3_Y_MODIFY 0xFFC01F9C	/*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
517
#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0	/*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
518
#define MDMA_D3_CURR_ADDR 0xFFC01FA4	/*MemDMA1 Stream 1 Dest Current Address */
519
#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0	/*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
520
#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8	/*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
521
#define MDMA_D3_IRQ_STATUS 0xFFC01FA8	/*MemDMA1 Stream 1 Dest Interrupt/Status */
522
#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC	/*MemDMA1 Stream 1 Dest Peripheral Map */
523

524
#define MDMA_S3_CONFIG 0xFFC01FC8	/*MemDMA1 Stream 1 Source Configuration */
525
#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0	/*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
526
#define MDMA_S3_START_ADDR 0xFFC01FC4	/*MemDMA1 Stream 1 Source Start Address */
527
#define MDMA_S3_X_COUNT 0xFFC01FD0	/*MemDMA1 Stream 1 Source Inner-Loop Count */
528
#define MDMA_S3_Y_COUNT 0xFFC01FD8	/*MemDMA1 Stream 1 Source Outer-Loop Count */
529
#define MDMA_S3_X_MODIFY 0xFFC01FD4	/*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
530
#define MDMA_S3_Y_MODIFY 0xFFC01FDC	/*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
531
#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0	/*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
532
#define MDMA_S3_CURR_ADDR 0xFFC01FE4	/*MemDMA1 Stream 1 Source Current Address */
533
#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0	/*MemDMA1 Stream 1 Source Current Inner-Loop Count */
534
#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8	/*MemDMA1 Stream 1 Source Current Outer-Loop Count */
535
#define MDMA_S3_IRQ_STATUS 0xFFC01FE8	/*MemDMA1 Stream 1 Source Interrupt/Status */
536
#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC	/*MemDMA1 Stream 1 Source Peripheral Map */
537

538
/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
539
#define DMA2_0_CONFIG 0xFFC00C08	/* DMA2 Channel 0 Configuration register */
540
#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00	/* DMA2 Channel 0 Next Descripter Ptr Reg */
541
#define DMA2_0_START_ADDR 0xFFC00C04	/* DMA2 Channel 0 Start Address */
542
#define DMA2_0_X_COUNT 0xFFC00C10	/* DMA2 Channel 0 Inner Loop Count */
543
#define DMA2_0_Y_COUNT 0xFFC00C18	/* DMA2 Channel 0 Outer Loop Count */
544
#define DMA2_0_X_MODIFY 0xFFC00C14	/* DMA2 Channel 0 Inner Loop Addr Increment */
545
#define DMA2_0_Y_MODIFY 0xFFC00C1C	/* DMA2 Channel 0 Outer Loop Addr Increment */
546
#define DMA2_0_CURR_DESC_PTR 0xFFC00C20	/* DMA2 Channel 0 Current Descriptor Pointer */
547
#define DMA2_0_CURR_ADDR 0xFFC00C24	/* DMA2 Channel 0 Current Address Pointer */
548
#define DMA2_0_CURR_X_COUNT 0xFFC00C30	/* DMA2 Channel 0 Current Inner Loop Count */
549
#define DMA2_0_CURR_Y_COUNT 0xFFC00C38	/* DMA2 Channel 0 Current Outer Loop Count */
550
#define DMA2_0_IRQ_STATUS 0xFFC00C28	/* DMA2 Channel 0 Interrupt/Status Register */
551
#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C	/* DMA2 Channel 0 Peripheral Map Register */
552

553
#define DMA2_1_CONFIG 0xFFC00C48	/* DMA2 Channel 1 Configuration register */
554
#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40	/* DMA2 Channel 1 Next Descripter Ptr Reg */
555
#define DMA2_1_START_ADDR 0xFFC00C44	/* DMA2 Channel 1 Start Address */
556
#define DMA2_1_X_COUNT 0xFFC00C50	/* DMA2 Channel 1 Inner Loop Count */
557
#define DMA2_1_Y_COUNT 0xFFC00C58	/* DMA2 Channel 1 Outer Loop Count */
558
#define DMA2_1_X_MODIFY 0xFFC00C54	/* DMA2 Channel 1 Inner Loop Addr Increment */
559
#define DMA2_1_Y_MODIFY 0xFFC00C5C	/* DMA2 Channel 1 Outer Loop Addr Increment */
560
#define DMA2_1_CURR_DESC_PTR 0xFFC00C60	/* DMA2 Channel 1 Current Descriptor Pointer */
561
#define DMA2_1_CURR_ADDR 0xFFC00C64	/* DMA2 Channel 1 Current Address Pointer */
562
#define DMA2_1_CURR_X_COUNT 0xFFC00C70	/* DMA2 Channel 1 Current Inner Loop Count */
563
#define DMA2_1_CURR_Y_COUNT 0xFFC00C78	/* DMA2 Channel 1 Current Outer Loop Count */
564
#define DMA2_1_IRQ_STATUS 0xFFC00C68	/* DMA2 Channel 1 Interrupt/Status Register */
565
#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C	/* DMA2 Channel 1 Peripheral Map Register */
566

567
#define DMA2_2_CONFIG 0xFFC00C88	/* DMA2 Channel 2 Configuration register */
568
#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80	/* DMA2 Channel 2 Next Descripter Ptr Reg */
569
#define DMA2_2_START_ADDR 0xFFC00C84	/* DMA2 Channel 2 Start Address */
570
#define DMA2_2_X_COUNT 0xFFC00C90	/* DMA2 Channel 2 Inner Loop Count */
571
#define DMA2_2_Y_COUNT 0xFFC00C98	/* DMA2 Channel 2 Outer Loop Count */
572
#define DMA2_2_X_MODIFY 0xFFC00C94	/* DMA2 Channel 2 Inner Loop Addr Increment */
573
#define DMA2_2_Y_MODIFY 0xFFC00C9C	/* DMA2 Channel 2 Outer Loop Addr Increment */
574
#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0	/* DMA2 Channel 2 Current Descriptor Pointer */
575
#define DMA2_2_CURR_ADDR 0xFFC00CA4	/* DMA2 Channel 2 Current Address Pointer */
576
#define DMA2_2_CURR_X_COUNT 0xFFC00CB0	/* DMA2 Channel 2 Current Inner Loop Count */
577
#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8	/* DMA2 Channel 2 Current Outer Loop Count */
578
#define DMA2_2_IRQ_STATUS 0xFFC00CA8	/* DMA2 Channel 2 Interrupt/Status Register */
579
#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC	/* DMA2 Channel 2 Peripheral Map Register */
580

581
#define DMA2_3_CONFIG 0xFFC00CC8	/* DMA2 Channel 3 Configuration register */
582
#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0	/* DMA2 Channel 3 Next Descripter Ptr Reg */
583
#define DMA2_3_START_ADDR 0xFFC00CC4	/* DMA2 Channel 3 Start Address */
584
#define DMA2_3_X_COUNT 0xFFC00CD0	/* DMA2 Channel 3 Inner Loop Count */
585
#define DMA2_3_Y_COUNT 0xFFC00CD8	/* DMA2 Channel 3 Outer Loop Count */
586
#define DMA2_3_X_MODIFY 0xFFC00CD4	/* DMA2 Channel 3 Inner Loop Addr Increment */
587
#define DMA2_3_Y_MODIFY 0xFFC00CDC	/* DMA2 Channel 3 Outer Loop Addr Increment */
588
#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0	/* DMA2 Channel 3 Current Descriptor Pointer */
589
#define DMA2_3_CURR_ADDR 0xFFC00CE4	/* DMA2 Channel 3 Current Address Pointer */
590
#define DMA2_3_CURR_X_COUNT 0xFFC00CF0	/* DMA2 Channel 3 Current Inner Loop Count */
591
#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8	/* DMA2 Channel 3 Current Outer Loop Count */
592
#define DMA2_3_IRQ_STATUS 0xFFC00CE8	/* DMA2 Channel 3 Interrupt/Status Register */
593
#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC	/* DMA2 Channel 3 Peripheral Map Register */
594

595
#define DMA2_4_CONFIG 0xFFC00D08	/* DMA2 Channel 4 Configuration register */
596
#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00	/* DMA2 Channel 4 Next Descripter Ptr Reg */
597
#define DMA2_4_START_ADDR 0xFFC00D04	/* DMA2 Channel 4 Start Address */
598
#define DMA2_4_X_COUNT 0xFFC00D10	/* DMA2 Channel 4 Inner Loop Count */
599
#define DMA2_4_Y_COUNT 0xFFC00D18	/* DMA2 Channel 4 Outer Loop Count */
600
#define DMA2_4_X_MODIFY 0xFFC00D14	/* DMA2 Channel 4 Inner Loop Addr Increment */
601
#define DMA2_4_Y_MODIFY 0xFFC00D1C	/* DMA2 Channel 4 Outer Loop Addr Increment */
602
#define DMA2_4_CURR_DESC_PTR 0xFFC00D20	/* DMA2 Channel 4 Current Descriptor Pointer */
603
#define DMA2_4_CURR_ADDR 0xFFC00D24	/* DMA2 Channel 4 Current Address Pointer */
604
#define DMA2_4_CURR_X_COUNT 0xFFC00D30	/* DMA2 Channel 4 Current Inner Loop Count */
605
#define DMA2_4_CURR_Y_COUNT 0xFFC00D38	/* DMA2 Channel 4 Current Outer Loop Count */
606
#define DMA2_4_IRQ_STATUS 0xFFC00D28	/* DMA2 Channel 4 Interrupt/Status Register */
607
#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C	/* DMA2 Channel 4 Peripheral Map Register */
608

609
#define DMA2_5_CONFIG 0xFFC00D48	/* DMA2 Channel 5 Configuration register */
610
#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40	/* DMA2 Channel 5 Next Descripter Ptr Reg */
611
#define DMA2_5_START_ADDR 0xFFC00D44	/* DMA2 Channel 5 Start Address */
612
#define DMA2_5_X_COUNT 0xFFC00D50	/* DMA2 Channel 5 Inner Loop Count */
613
#define DMA2_5_Y_COUNT 0xFFC00D58	/* DMA2 Channel 5 Outer Loop Count */
614
#define DMA2_5_X_MODIFY 0xFFC00D54	/* DMA2 Channel 5 Inner Loop Addr Increment */
615
#define DMA2_5_Y_MODIFY 0xFFC00D5C	/* DMA2 Channel 5 Outer Loop Addr Increment */
616
#define DMA2_5_CURR_DESC_PTR 0xFFC00D60	/* DMA2 Channel 5 Current Descriptor Pointer */
617
#define DMA2_5_CURR_ADDR 0xFFC00D64	/* DMA2 Channel 5 Current Address Pointer */
618
#define DMA2_5_CURR_X_COUNT 0xFFC00D70	/* DMA2 Channel 5 Current Inner Loop Count */
619
#define DMA2_5_CURR_Y_COUNT 0xFFC00D78	/* DMA2 Channel 5 Current Outer Loop Count */
620
#define DMA2_5_IRQ_STATUS 0xFFC00D68	/* DMA2 Channel 5 Interrupt/Status Register */
621
#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C	/* DMA2 Channel 5 Peripheral Map Register */
622

623
#define DMA2_6_CONFIG 0xFFC00D88	/* DMA2 Channel 6 Configuration register */
624
#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80	/* DMA2 Channel 6 Next Descripter Ptr Reg */
625
#define DMA2_6_START_ADDR 0xFFC00D84	/* DMA2 Channel 6 Start Address */
626
#define DMA2_6_X_COUNT 0xFFC00D90	/* DMA2 Channel 6 Inner Loop Count */
627
#define DMA2_6_Y_COUNT 0xFFC00D98	/* DMA2 Channel 6 Outer Loop Count */
628
#define DMA2_6_X_MODIFY 0xFFC00D94	/* DMA2 Channel 6 Inner Loop Addr Increment */
629
#define DMA2_6_Y_MODIFY 0xFFC00D9C	/* DMA2 Channel 6 Outer Loop Addr Increment */
630
#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0	/* DMA2 Channel 6 Current Descriptor Pointer */
631
#define DMA2_6_CURR_ADDR 0xFFC00DA4	/* DMA2 Channel 6 Current Address Pointer */
632
#define DMA2_6_CURR_X_COUNT 0xFFC00DB0	/* DMA2 Channel 6 Current Inner Loop Count */
633
#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8	/* DMA2 Channel 6 Current Outer Loop Count */
634
#define DMA2_6_IRQ_STATUS 0xFFC00DA8	/* DMA2 Channel 6 Interrupt/Status Register */
635
#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC	/* DMA2 Channel 6 Peripheral Map Register */
636

637
#define DMA2_7_CONFIG 0xFFC00DC8	/* DMA2 Channel 7 Configuration register */
638
#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0	/* DMA2 Channel 7 Next Descripter Ptr Reg */
639
#define DMA2_7_START_ADDR 0xFFC00DC4	/* DMA2 Channel 7 Start Address */
640
#define DMA2_7_X_COUNT 0xFFC00DD0	/* DMA2 Channel 7 Inner Loop Count */
641
#define DMA2_7_Y_COUNT 0xFFC00DD8	/* DMA2 Channel 7 Outer Loop Count */
642
#define DMA2_7_X_MODIFY 0xFFC00DD4	/* DMA2 Channel 7 Inner Loop Addr Increment */
643
#define DMA2_7_Y_MODIFY 0xFFC00DDC	/* DMA2 Channel 7 Outer Loop Addr Increment */
644
#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0	/* DMA2 Channel 7 Current Descriptor Pointer */
645
#define DMA2_7_CURR_ADDR 0xFFC00DE4	/* DMA2 Channel 7 Current Address Pointer */
646
#define DMA2_7_CURR_X_COUNT 0xFFC00DF0	/* DMA2 Channel 7 Current Inner Loop Count */
647
#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8	/* DMA2 Channel 7 Current Outer Loop Count */
648
#define DMA2_7_IRQ_STATUS 0xFFC00DE8	/* DMA2 Channel 7 Interrupt/Status Register */
649
#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC	/* DMA2 Channel 7 Peripheral Map Register */
650

651
#define DMA2_8_CONFIG 0xFFC00E08	/* DMA2 Channel 8 Configuration register */
652
#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00	/* DMA2 Channel 8 Next Descripter Ptr Reg */
653
#define DMA2_8_START_ADDR 0xFFC00E04	/* DMA2 Channel 8 Start Address */
654
#define DMA2_8_X_COUNT 0xFFC00E10	/* DMA2 Channel 8 Inner Loop Count */
655
#define DMA2_8_Y_COUNT 0xFFC00E18	/* DMA2 Channel 8 Outer Loop Count */
656
#define DMA2_8_X_MODIFY 0xFFC00E14	/* DMA2 Channel 8 Inner Loop Addr Increment */
657
#define DMA2_8_Y_MODIFY 0xFFC00E1C	/* DMA2 Channel 8 Outer Loop Addr Increment */
658
#define DMA2_8_CURR_DESC_PTR 0xFFC00E20	/* DMA2 Channel 8 Current Descriptor Pointer */
659
#define DMA2_8_CURR_ADDR 0xFFC00E24	/* DMA2 Channel 8 Current Address Pointer */
660
#define DMA2_8_CURR_X_COUNT 0xFFC00E30	/* DMA2 Channel 8 Current Inner Loop Count */
661
#define DMA2_8_CURR_Y_COUNT 0xFFC00E38	/* DMA2 Channel 8 Current Outer Loop Count */
662
#define DMA2_8_IRQ_STATUS 0xFFC00E28	/* DMA2 Channel 8 Interrupt/Status Register */
663
#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C	/* DMA2 Channel 8 Peripheral Map Register */
664

665
#define DMA2_9_CONFIG 0xFFC00E48	/* DMA2 Channel 9 Configuration register */
666
#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40	/* DMA2 Channel 9 Next Descripter Ptr Reg */
667
#define DMA2_9_START_ADDR 0xFFC00E44	/* DMA2 Channel 9 Start Address */
668
#define DMA2_9_X_COUNT 0xFFC00E50	/* DMA2 Channel 9 Inner Loop Count */
669
#define DMA2_9_Y_COUNT 0xFFC00E58	/* DMA2 Channel 9 Outer Loop Count */
670
#define DMA2_9_X_MODIFY 0xFFC00E54	/* DMA2 Channel 9 Inner Loop Addr Increment */
671
#define DMA2_9_Y_MODIFY 0xFFC00E5C	/* DMA2 Channel 9 Outer Loop Addr Increment */
672
#define DMA2_9_CURR_DESC_PTR 0xFFC00E60	/* DMA2 Channel 9 Current Descriptor Pointer */
673
#define DMA2_9_CURR_ADDR 0xFFC00E64	/* DMA2 Channel 9 Current Address Pointer */
674
#define DMA2_9_CURR_X_COUNT 0xFFC00E70	/* DMA2 Channel 9 Current Inner Loop Count */
675
#define DMA2_9_CURR_Y_COUNT 0xFFC00E78	/* DMA2 Channel 9 Current Outer Loop Count */
676
#define DMA2_9_IRQ_STATUS 0xFFC00E68	/* DMA2 Channel 9 Interrupt/Status Register */
677
#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C	/* DMA2 Channel 9 Peripheral Map Register */
678

679
#define DMA2_10_CONFIG 0xFFC00E88	/* DMA2 Channel 10 Configuration register */
680
#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80	/* DMA2 Channel 10 Next Descripter Ptr Reg */
681
#define DMA2_10_START_ADDR 0xFFC00E84	/* DMA2 Channel 10 Start Address */
682
#define DMA2_10_X_COUNT 0xFFC00E90	/* DMA2 Channel 10 Inner Loop Count */
683
#define DMA2_10_Y_COUNT 0xFFC00E98	/* DMA2 Channel 10 Outer Loop Count */
684
#define DMA2_10_X_MODIFY 0xFFC00E94	/* DMA2 Channel 10 Inner Loop Addr Increment */
685
#define DMA2_10_Y_MODIFY 0xFFC00E9C	/* DMA2 Channel 10 Outer Loop Addr Increment */
686
#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0	/* DMA2 Channel 10 Current Descriptor Pointer */
687
#define DMA2_10_CURR_ADDR 0xFFC00EA4	/* DMA2 Channel 10 Current Address Pointer */
688
#define DMA2_10_CURR_X_COUNT 0xFFC00EB0	/* DMA2 Channel 10 Current Inner Loop Count */
689
#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8	/* DMA2 Channel 10 Current Outer Loop Count */
690
#define DMA2_10_IRQ_STATUS 0xFFC00EA8	/* DMA2 Channel 10 Interrupt/Status Register */
691
#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC	/* DMA2 Channel 10 Peripheral Map Register */
692

693
#define DMA2_11_CONFIG 0xFFC00EC8	/* DMA2 Channel 11 Configuration register */
694
#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0	/* DMA2 Channel 11 Next Descripter Ptr Reg */
695
#define DMA2_11_START_ADDR 0xFFC00EC4	/* DMA2 Channel 11 Start Address */
696
#define DMA2_11_X_COUNT 0xFFC00ED0	/* DMA2 Channel 11 Inner Loop Count */
697
#define DMA2_11_Y_COUNT 0xFFC00ED8	/* DMA2 Channel 11 Outer Loop Count */
698
#define DMA2_11_X_MODIFY 0xFFC00ED4	/* DMA2 Channel 11 Inner Loop Addr Increment */
699
#define DMA2_11_Y_MODIFY 0xFFC00EDC	/* DMA2 Channel 11 Outer Loop Addr Increment */
700
#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0	/* DMA2 Channel 11 Current Descriptor Pointer */
701
#define DMA2_11_CURR_ADDR 0xFFC00EE4	/* DMA2 Channel 11 Current Address Pointer */
702
#define DMA2_11_CURR_X_COUNT 0xFFC00EF0	/* DMA2 Channel 11 Current Inner Loop Count */
703
#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8	/* DMA2 Channel 11 Current Outer Loop Count */
704
#define DMA2_11_IRQ_STATUS 0xFFC00EE8	/* DMA2 Channel 11 Interrupt/Status Register */
705
#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC	/* DMA2 Channel 11 Peripheral Map Register */
706

707
/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
708
#define MDMA_D0_CONFIG 0xFFC00F08	/*MemDMA2 Stream 0 Destination Configuration register */
709
#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00	/*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
710
#define MDMA_D0_START_ADDR 0xFFC00F04	/*MemDMA2 Stream 0 Destination Start Address */
711
#define MDMA_D0_X_COUNT 0xFFC00F10	/*MemDMA2 Stream 0 Dest Inner-Loop Count register */
712
#define MDMA_D0_Y_COUNT 0xFFC00F18	/*MemDMA2 Stream 0 Dest Outer-Loop Count register */
713
#define MDMA_D0_X_MODIFY 0xFFC00F14	/*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
714
#define MDMA_D0_Y_MODIFY 0xFFC00F1C	/*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
715
#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20	/*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
716
#define MDMA_D0_CURR_ADDR 0xFFC00F24	/*MemDMA2 Stream 0 Destination Current Address */
717
#define MDMA_D0_CURR_X_COUNT 0xFFC00F30	/*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
718
#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38	/*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
719
#define MDMA_D0_IRQ_STATUS 0xFFC00F28	/*MemDMA2 Stream 0 Dest Interrupt/Status Register */
720
#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C	/*MemDMA2 Stream 0 Destination Peripheral Map register */
721

722
#define MDMA_S0_CONFIG 0xFFC00F48	/*MemDMA2 Stream 0 Source Configuration register */
723
#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40	/*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
724
#define MDMA_S0_START_ADDR 0xFFC00F44	/*MemDMA2 Stream 0 Source Start Address */
725
#define MDMA_S0_X_COUNT 0xFFC00F50	/*MemDMA2 Stream 0 Source Inner-Loop Count register */
726
#define MDMA_S0_Y_COUNT 0xFFC00F58	/*MemDMA2 Stream 0 Source Outer-Loop Count register */
727
#define MDMA_S0_X_MODIFY 0xFFC00F54	/*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
728
#define MDMA_S0_Y_MODIFY 0xFFC00F5C	/*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
729
#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60	/*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
730
#define MDMA_S0_CURR_ADDR 0xFFC00F64	/*MemDMA2 Stream 0 Source Current Address */
731
#define MDMA_S0_CURR_X_COUNT 0xFFC00F70	/*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
732
#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78	/*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
733
#define MDMA_S0_IRQ_STATUS 0xFFC00F68	/*MemDMA2 Stream 0 Source Interrupt/Status Register */
734
#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C	/*MemDMA2 Stream 0 Source Peripheral Map register */
735

736
#define MDMA_D1_CONFIG 0xFFC00F88	/*MemDMA2 Stream 1 Destination Configuration register */
737
#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80	/*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
738
#define MDMA_D1_START_ADDR 0xFFC00F84	/*MemDMA2 Stream 1 Destination Start Address */
739
#define MDMA_D1_X_COUNT 0xFFC00F90	/*MemDMA2 Stream 1 Dest Inner-Loop Count register */
740
#define MDMA_D1_Y_COUNT 0xFFC00F98	/*MemDMA2 Stream 1 Dest Outer-Loop Count register */
741
#define MDMA_D1_X_MODIFY 0xFFC00F94	/*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
742
#define MDMA_D1_Y_MODIFY 0xFFC00F9C	/*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
743
#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0	/*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
744
#define MDMA_D1_CURR_ADDR 0xFFC00FA4	/*MemDMA2 Stream 1 Destination Current Address reg */
745
#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0	/*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
746
#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8	/*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
747
#define MDMA_D1_IRQ_STATUS 0xFFC00FA8	/*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
748
#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC	/*MemDMA2 Stream 1 Destination Peripheral Map register */
749

750
#define MDMA_S1_CONFIG 0xFFC00FC8	/*MemDMA2 Stream 1 Source Configuration register */
751
#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0	/*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
752
#define MDMA_S1_START_ADDR 0xFFC00FC4	/*MemDMA2 Stream 1 Source Start Address */
753
#define MDMA_S1_X_COUNT 0xFFC00FD0	/*MemDMA2 Stream 1 Source Inner-Loop Count register */
754
#define MDMA_S1_Y_COUNT 0xFFC00FD8	/*MemDMA2 Stream 1 Source Outer-Loop Count register */
755
#define MDMA_S1_X_MODIFY 0xFFC00FD4	/*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
756
#define MDMA_S1_Y_MODIFY 0xFFC00FDC	/*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
757
#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0	/*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
758
#define MDMA_S1_CURR_ADDR 0xFFC00FE4	/*MemDMA2 Stream 1 Source Current Address */
759
#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0	/*MemDMA2 Stream 1 Source Current Inner-Loop Count */
760
#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8	/*MemDMA2 Stream 1 Source Current Outer-Loop Count */
761
#define MDMA_S1_IRQ_STATUS 0xFFC00FE8	/*MemDMA2 Stream 1 Source Interrupt/Status Register */
762
#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC	/*MemDMA2 Stream 1 Source Peripheral Map register */
763

764
/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
765
#define IMDMA_D0_CONFIG 0xFFC01808	/*IMDMA Stream 0 Destination Configuration */
766
#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800	/*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
767
#define IMDMA_D0_START_ADDR 0xFFC01804	/*IMDMA Stream 0 Destination Start Address */
768
#define IMDMA_D0_X_COUNT 0xFFC01810	/*IMDMA Stream 0 Destination Inner-Loop Count */
769
#define IMDMA_D0_Y_COUNT 0xFFC01818	/*IMDMA Stream 0 Destination Outer-Loop Count */
770
#define IMDMA_D0_X_MODIFY 0xFFC01814	/*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
771
#define IMDMA_D0_Y_MODIFY 0xFFC0181C	/*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
772
#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820	/*IMDMA Stream 0 Destination Current Descriptor Ptr */
773
#define IMDMA_D0_CURR_ADDR 0xFFC01824	/*IMDMA Stream 0 Destination Current Address */
774
#define IMDMA_D0_CURR_X_COUNT 0xFFC01830	/*IMDMA Stream 0 Destination Current Inner-Loop Count */
775
#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838	/*IMDMA Stream 0 Destination Current Outer-Loop Count */
776
#define IMDMA_D0_IRQ_STATUS 0xFFC01828	/*IMDMA Stream 0 Destination Interrupt/Status */
777

778
#define IMDMA_S0_CONFIG 0xFFC01848	/*IMDMA Stream 0 Source Configuration */
779
#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840	/*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
780
#define IMDMA_S0_START_ADDR 0xFFC01844	/*IMDMA Stream 0 Source Start Address */
781
#define IMDMA_S0_X_COUNT 0xFFC01850	/*IMDMA Stream 0 Source Inner-Loop Count */
782
#define IMDMA_S0_Y_COUNT 0xFFC01858	/*IMDMA Stream 0 Source Outer-Loop Count */
783
#define IMDMA_S0_X_MODIFY 0xFFC01854	/*IMDMA Stream 0 Source Inner-Loop Address-Increment */
784
#define IMDMA_S0_Y_MODIFY 0xFFC0185C	/*IMDMA Stream 0 Source Outer-Loop Address-Increment */
785
#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860	/*IMDMA Stream 0 Source Current Descriptor Ptr reg */
786
#define IMDMA_S0_CURR_ADDR 0xFFC01864	/*IMDMA Stream 0 Source Current Address */
787
#define IMDMA_S0_CURR_X_COUNT 0xFFC01870	/*IMDMA Stream 0 Source Current Inner-Loop Count */
788
#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878	/*IMDMA Stream 0 Source Current Outer-Loop Count */
789
#define IMDMA_S0_IRQ_STATUS 0xFFC01868	/*IMDMA Stream 0 Source Interrupt/Status */
790

791
#define IMDMA_D1_CONFIG 0xFFC01888	/*IMDMA Stream 1 Destination Configuration */
792
#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880	/*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
793
#define IMDMA_D1_START_ADDR 0xFFC01884	/*IMDMA Stream 1 Destination Start Address */
794
#define IMDMA_D1_X_COUNT 0xFFC01890	/*IMDMA Stream 1 Destination Inner-Loop Count */
795
#define IMDMA_D1_Y_COUNT 0xFFC01898	/*IMDMA Stream 1 Destination Outer-Loop Count */
796
#define IMDMA_D1_X_MODIFY 0xFFC01894	/*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
797
#define IMDMA_D1_Y_MODIFY 0xFFC0189C	/*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
798
#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0	/*IMDMA Stream 1 Destination Current Descriptor Ptr */
799
#define IMDMA_D1_CURR_ADDR 0xFFC018A4	/*IMDMA Stream 1 Destination Current Address */
800
#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0	/*IMDMA Stream 1 Destination Current Inner-Loop Count */
801
#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8	/*IMDMA Stream 1 Destination Current Outer-Loop Count */
802
#define IMDMA_D1_IRQ_STATUS 0xFFC018A8	/*IMDMA Stream 1 Destination Interrupt/Status */
803

804
#define IMDMA_S1_CONFIG 0xFFC018C8	/*IMDMA Stream 1 Source Configuration */
805
#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0	/*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
806
#define IMDMA_S1_START_ADDR 0xFFC018C4	/*IMDMA Stream 1 Source Start Address */
807
#define IMDMA_S1_X_COUNT 0xFFC018D0	/*IMDMA Stream 1 Source Inner-Loop Count */
808
#define IMDMA_S1_Y_COUNT 0xFFC018D8	/*IMDMA Stream 1 Source Outer-Loop Count */
809
#define IMDMA_S1_X_MODIFY 0xFFC018D4	/*IMDMA Stream 1 Source Inner-Loop Address-Increment */
810
#define IMDMA_S1_Y_MODIFY 0xFFC018DC	/*IMDMA Stream 1 Source Outer-Loop Address-Increment */
811
#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0	/*IMDMA Stream 1 Source Current Descriptor Ptr reg */
812
#define IMDMA_S1_CURR_ADDR 0xFFC018E4	/*IMDMA Stream 1 Source Current Address */
813
#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0	/*IMDMA Stream 1 Source Current Inner-Loop Count */
814
#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8	/*IMDMA Stream 1 Source Current Outer-Loop Count */
815
#define IMDMA_S1_IRQ_STATUS 0xFFC018E8	/*IMDMA Stream 1 Source Interrupt/Status */
816

817
/*********************************************************************************** */
818
/* System MMR Register Bits */
819
/******************************************************************************* */
820

821
/* CHIPID Masks */
822
#define CHIPID_VERSION         0xF0000000
823
#define CHIPID_FAMILY          0x0FFFF000
824
#define CHIPID_MANUFACTURE     0x00000FFE
825

826
/* SICA_SYSCR Masks */
827
#define COREB_SRAM_INIT		0x0020
828

829
/* SWRST Mask */
830
#define SYSTEM_RESET           0x0007	/* Initiates a system software reset */
831
#define DOUBLE_FAULT_A         0x0008	/* Core A Double Fault Causes Reset */
832
#define DOUBLE_FAULT_B         0x0010	/* Core B Double Fault Causes Reset */
833
#define SWRST_DBL_FAULT_A      0x0800	/* SWRST Core A Double Fault */
834
#define SWRST_DBL_FAULT_B      0x1000	/* SWRST Core B Double Fault */
835
#define SWRST_WDT_B		       0x2000	/* SWRST Watchdog B */
836
#define SWRST_WDT_A		       0x4000	/* SWRST Watchdog A */
837
#define SWRST_OCCURRED         0x8000	/* SWRST Status */
838

839
/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
840

841
/* SICu_IARv Masks	 */
842
/* u = A or B */
843
/* v = 0 to 7 */
844
/* w = 0 or 1 */
845

846
/* Per_number = 0 to 63 */
847
/* IVG_number = 7 to 15   */
848
#define Peripheral_IVG(Per_number, IVG_number)    \
849
    ((IVG_number) - 7) << (((Per_number) % 8) * 4)	/* Peripheral #Per_number assigned IVG #IVG_number  */
850
    /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
851
    /*        r0.h = hi(Peripheral_IVG(62, 10)); */
852

853
/* SICx_IMASKw Masks */
854
/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers  */
855
#define SIC_UNMASK_ALL         0x00000000	/* Unmask all peripheral interrupts */
856
#define SIC_MASK_ALL           0xFFFFFFFF	/* Mask all peripheral interrupts */
857
#define SIC_MASK(x)	       (1 << (x))	/* Mask Peripheral #x interrupt */
858
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x)))	/* Unmask Peripheral #x interrupt */
859

860
/* SIC_IWR Masks */
861
#define IWR_DISABLE_ALL        0x00000000	/* Wakeup Disable all peripherals */
862
#define IWR_ENABLE_ALL         0xFFFFFFFF	/* Wakeup Enable all peripherals */
863
/* x = pos 0 to 31, for 32-63 use value-32 */
864
#define IWR_ENABLE(x)	       (1 << (x))	/* Wakeup Enable Peripheral #x */
865
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))	/* Wakeup Disable Peripheral #x */
866

867
/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
868

869
/*  PPI_CONTROL Masks         */
870
#define PORT_EN              0x00000001	/* PPI Port Enable  */
871
#define PORT_DIR             0x00000002	/* PPI Port Direction       */
872
#define XFR_TYPE             0x0000000C	/* PPI Transfer Type  */
873
#define PORT_CFG             0x00000030	/* PPI Port Configuration */
874
#define FLD_SEL              0x00000040	/* PPI Active Field Select */
875
#define PACK_EN              0x00000080	/* PPI Packing Mode */
876
#define DMA32                0x00000100	/* PPI 32-bit DMA Enable */
877
#define SKIP_EN              0x00000200	/* PPI Skip Element Enable */
878
#define SKIP_EO              0x00000400	/* PPI Skip Even/Odd Elements */
879
#define DLENGTH              0x00003800	/* PPI Data Length  */
880
#define DLEN_8		     0x0	/* PPI Data Length mask for DLEN=8 */
881
#define DLEN(x)	(((x-9) & 0x07) << 11)	/* PPI Data Length (only works for x=10-->x=16) */
882
#define POL                  0x0000C000	/* PPI Signal Polarities       */
883
#define	POLC		0x4000		/* PPI Clock Polarity */
884
#define	POLS		0x8000		/* PPI Frame Sync Polarity */
885

886
/* PPI_STATUS Masks */
887
#define FLD	             0x00000400	/* Field Indicator   */
888
#define FT_ERR	             0x00000800	/* Frame Track Error */
889
#define OVR	             0x00001000	/* FIFO Overflow Error */
890
#define UNDR	             0x00002000	/* FIFO Underrun Error */
891
#define ERR_DET	      	     0x00004000	/* Error Detected Indicator */
892
#define ERR_NCOR	     0x00008000	/* Error Not Corrected Indicator */
893

894
/* **********  DMA CONTROLLER MASKS  *********************8 */
895

896
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
897

898
#define CTYPE	            0x00000040	/* DMA Channel Type Indicator */
899
#define CTYPE_P             6	/* DMA Channel Type Indicator BIT POSITION */
900
#define PCAP8	            0x00000080	/* DMA 8-bit Operation Indicator   */
901
#define PCAP16	            0x00000100	/* DMA 16-bit Operation Indicator */
902
#define PCAP32	            0x00000200	/* DMA 32-bit Operation Indicator */
903
#define PCAPWR	            0x00000400	/* DMA Write Operation Indicator */
904
#define PCAPRD	            0x00000800	/* DMA Read Operation Indicator */
905
#define PMAP	            0x00007000	/* DMA Peripheral Map Field */
906

907
/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
908

909
/* PWM Timer bit definitions */
910

911
/* TIMER_ENABLE Register */
912
#define TIMEN0	0x0001
913
#define TIMEN1	0x0002
914
#define TIMEN2	0x0004
915
#define TIMEN3	0x0008
916
#define TIMEN4	0x0010
917
#define TIMEN5	0x0020
918
#define TIMEN6	0x0040
919
#define TIMEN7	0x0080
920
#define TIMEN8	0x0001
921
#define TIMEN9	0x0002
922
#define TIMEN10	0x0004
923
#define TIMEN11	0x0008
924

925
#define TIMEN0_P	0x00
926
#define TIMEN1_P	0x01
927
#define TIMEN2_P	0x02
928
#define TIMEN3_P	0x03
929
#define TIMEN4_P	0x04
930
#define TIMEN5_P	0x05
931
#define TIMEN6_P	0x06
932
#define TIMEN7_P	0x07
933
#define TIMEN8_P	0x00
934
#define TIMEN9_P	0x01
935
#define TIMEN10_P	0x02
936
#define TIMEN11_P	0x03
937

938
/* TIMER_DISABLE Register */
939
#define TIMDIS0		0x0001
940
#define TIMDIS1		0x0002
941
#define TIMDIS2		0x0004
942
#define TIMDIS3		0x0008
943
#define TIMDIS4		0x0010
944
#define TIMDIS5		0x0020
945
#define TIMDIS6		0x0040
946
#define TIMDIS7		0x0080
947
#define TIMDIS8		0x0001
948
#define TIMDIS9		0x0002
949
#define TIMDIS10	0x0004
950
#define TIMDIS11	0x0008
951

952
#define TIMDIS0_P	0x00
953
#define TIMDIS1_P	0x01
954
#define TIMDIS2_P	0x02
955
#define TIMDIS3_P	0x03
956
#define TIMDIS4_P	0x04
957
#define TIMDIS5_P	0x05
958
#define TIMDIS6_P	0x06
959
#define TIMDIS7_P	0x07
960
#define TIMDIS8_P	0x00
961
#define TIMDIS9_P	0x01
962
#define TIMDIS10_P	0x02
963
#define TIMDIS11_P	0x03
964

965
/* TIMER_STATUS Register */
966
#define TIMIL0		0x00000001
967
#define TIMIL1		0x00000002
968
#define TIMIL2		0x00000004
969
#define TIMIL3		0x00000008
970
#define TIMIL4		0x00010000
971
#define TIMIL5		0x00020000
972
#define TIMIL6		0x00040000
973
#define TIMIL7		0x00080000
974
#define TIMIL8		0x0001
975
#define TIMIL9		0x0002
976
#define TIMIL10		0x0004
977
#define TIMIL11		0x0008
978
#define TOVF_ERR0	0x00000010
979
#define TOVF_ERR1	0x00000020
980
#define TOVF_ERR2	0x00000040
981
#define TOVF_ERR3	0x00000080
982
#define TOVF_ERR4	0x00100000
983
#define TOVF_ERR5	0x00200000
984
#define TOVF_ERR6	0x00400000
985
#define TOVF_ERR7	0x00800000
986
#define TOVF_ERR8	0x0010
987
#define TOVF_ERR9	0x0020
988
#define TOVF_ERR10	0x0040
989
#define TOVF_ERR11	0x0080
990
#define TRUN0		0x00001000
991
#define TRUN1		0x00002000
992
#define TRUN2		0x00004000
993
#define TRUN3		0x00008000
994
#define TRUN4		0x10000000
995
#define TRUN5		0x20000000
996
#define TRUN6		0x40000000
997
#define TRUN7		0x80000000
998
#define TRUN8		0x1000
999
#define TRUN9		0x2000
1000
#define TRUN10		0x4000
1001
#define TRUN11		0x8000
1002

1003
#define TIMIL0_P	0x00
1004
#define TIMIL1_P	0x01
1005
#define TIMIL2_P	0x02
1006
#define TIMIL3_P	0x03
1007
#define TIMIL4_P	0x10
1008
#define TIMIL5_P	0x11
1009
#define TIMIL6_P	0x12
1010
#define TIMIL7_P	0x13
1011
#define TIMIL8_P	0x00
1012
#define TIMIL9_P	0x01
1013
#define TIMIL10_P	0x02
1014
#define TIMIL11_P	0x03
1015
#define TOVF_ERR0_P	0x04
1016
#define TOVF_ERR1_P	0x05
1017
#define TOVF_ERR2_P	0x06
1018
#define TOVF_ERR3_P	0x07
1019
#define TOVF_ERR4_P	0x14
1020
#define TOVF_ERR5_P	0x15
1021
#define TOVF_ERR6_P	0x16
1022
#define TOVF_ERR7_P	0x17
1023
#define TOVF_ERR8_P	0x04
1024
#define TOVF_ERR9_P	0x05
1025
#define TOVF_ERR10_P	0x06
1026
#define TOVF_ERR11_P	0x07
1027
#define TRUN0_P		0x0C
1028
#define TRUN1_P		0x0D
1029
#define TRUN2_P		0x0E
1030
#define TRUN3_P		0x0F
1031
#define TRUN4_P		0x1C
1032
#define TRUN5_P		0x1D
1033
#define TRUN6_P		0x1E
1034
#define TRUN7_P		0x1F
1035
#define TRUN8_P		0x0C
1036
#define TRUN9_P		0x0D
1037
#define TRUN10_P	0x0E
1038
#define TRUN11_P	0x0F
1039

1040
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1041
#define TOVL_ERR0 TOVF_ERR0
1042
#define TOVL_ERR1 TOVF_ERR1
1043
#define TOVL_ERR2 TOVF_ERR2
1044
#define TOVL_ERR3 TOVF_ERR3
1045
#define TOVL_ERR4 TOVF_ERR4
1046
#define TOVL_ERR5 TOVF_ERR5
1047
#define TOVL_ERR6 TOVF_ERR6
1048
#define TOVL_ERR7 TOVF_ERR7
1049
#define TOVL_ERR8 TOVF_ERR8
1050
#define TOVL_ERR9 TOVF_ERR9
1051
#define TOVL_ERR10 TOVF_ERR10
1052
#define TOVL_ERR11 TOVF_ERR11
1053
#define TOVL_ERR0_P TOVF_ERR0_P
1054
#define TOVL_ERR1_P TOVF_ERR1_P
1055
#define TOVL_ERR2_P TOVF_ERR2_P
1056
#define TOVL_ERR3_P TOVF_ERR3_P
1057
#define TOVL_ERR4_P TOVF_ERR4_P
1058
#define TOVL_ERR5_P TOVF_ERR5_P
1059
#define TOVL_ERR6_P TOVF_ERR6_P
1060
#define TOVL_ERR7_P TOVF_ERR7_P
1061
#define TOVL_ERR8_P TOVF_ERR8_P
1062
#define TOVL_ERR9_P TOVF_ERR9_P
1063
#define TOVL_ERR10_P TOVF_ERR10_P
1064
#define TOVL_ERR11_P TOVF_ERR11_P
1065

1066
/* TIMERx_CONFIG Registers */
1067
#define PWM_OUT		0x0001
1068
#define WDTH_CAP	0x0002
1069
#define EXT_CLK		0x0003
1070
#define PULSE_HI	0x0004
1071
#define PERIOD_CNT	0x0008
1072
#define IRQ_ENA		0x0010
1073
#define TIN_SEL		0x0020
1074
#define OUT_DIS		0x0040
1075
#define CLK_SEL		0x0080
1076
#define TOGGLE_HI	0x0100
1077
#define EMU_RUN		0x0200
1078
#define ERR_TYP(x)	((x & 0x03) << 14)
1079

1080
#define TMODE_P0		0x00
1081
#define TMODE_P1		0x01
1082
#define PULSE_HI_P		0x02
1083
#define PERIOD_CNT_P		0x03
1084
#define IRQ_ENA_P		0x04
1085
#define TIN_SEL_P		0x05
1086
#define OUT_DIS_P		0x06
1087
#define CLK_SEL_P		0x07
1088
#define TOGGLE_HI_P		0x08
1089
#define EMU_RUN_P		0x09
1090
#define ERR_TYP_P0		0x0E
1091
#define ERR_TYP_P1		0x0F
1092

1093
/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
1094

1095
/* AMGCTL Masks */
1096
#define AMCKEN			0x0001	/* Enable CLKOUT */
1097
#define AMBEN_B0		0x0002	/* Enable Asynchronous Memory Bank 0 only */
1098
#define AMBEN_B0_B1		0x0004	/* Enable Asynchronous Memory Banks 0 & 1 only */
1099
#define AMBEN_B0_B1_B2	0x0006	/* Enable Asynchronous Memory Banks 0, 1, and 2 */
1100
#define AMBEN_ALL		0x0008	/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1101
#define B0_PEN			0x0010	/* Enable 16-bit packing Bank 0  */
1102
#define B1_PEN			0x0020	/* Enable 16-bit packing Bank 1  */
1103
#define B2_PEN			0x0040	/* Enable 16-bit packing Bank 2  */
1104
#define B3_PEN			0x0080	/* Enable 16-bit packing Bank 3  */
1105

1106
/* AMGCTL Bit Positions */
1107
#define AMCKEN_P		0x00000000	/* Enable CLKOUT */
1108
#define AMBEN_P0		0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1109
#define AMBEN_P1		0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
1110
#define AMBEN_P2		0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1111
#define B0_PEN_P			0x004	/* Enable 16-bit packing Bank 0  */
1112
#define B1_PEN_P			0x005	/* Enable 16-bit packing Bank 1  */
1113
#define B2_PEN_P			0x006	/* Enable 16-bit packing Bank 2  */
1114
#define B3_PEN_P			0x007	/* Enable 16-bit packing Bank 3  */
1115

1116
/* AMBCTL0 Masks */
1117
#define B0RDYEN	0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */
1118
#define B0RDYPOL 0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */
1119
#define B0TT_1	0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */
1120
#define B0TT_2	0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */
1121
#define B0TT_3	0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */
1122
#define B0TT_4	0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */
1123
#define B0ST_1	0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1124
#define B0ST_2	0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1125
#define B0ST_3	0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1126
#define B0ST_4	0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1127
#define B0HT_1	0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1128
#define B0HT_2	0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1129
#define B0HT_3	0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1130
#define B0HT_0	0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1131
#define B0RAT_1			0x00000100	/* Bank 0 Read Access Time = 1 cycle */
1132
#define B0RAT_2			0x00000200	/* Bank 0 Read Access Time = 2 cycles */
1133
#define B0RAT_3			0x00000300	/* Bank 0 Read Access Time = 3 cycles */
1134
#define B0RAT_4			0x00000400	/* Bank 0 Read Access Time = 4 cycles */
1135
#define B0RAT_5			0x00000500	/* Bank 0 Read Access Time = 5 cycles */
1136
#define B0RAT_6			0x00000600	/* Bank 0 Read Access Time = 6 cycles */
1137
#define B0RAT_7			0x00000700	/* Bank 0 Read Access Time = 7 cycles */
1138
#define B0RAT_8			0x00000800	/* Bank 0 Read Access Time = 8 cycles */
1139
#define B0RAT_9			0x00000900	/* Bank 0 Read Access Time = 9 cycles */
1140
#define B0RAT_10		0x00000A00	/* Bank 0 Read Access Time = 10 cycles */
1141
#define B0RAT_11		0x00000B00	/* Bank 0 Read Access Time = 11 cycles */
1142
#define B0RAT_12		0x00000C00	/* Bank 0 Read Access Time = 12 cycles */
1143
#define B0RAT_13		0x00000D00	/* Bank 0 Read Access Time = 13 cycles */
1144
#define B0RAT_14		0x00000E00	/* Bank 0 Read Access Time = 14 cycles */
1145
#define B0RAT_15		0x00000F00	/* Bank 0 Read Access Time = 15 cycles */
1146
#define B0WAT_1			0x00001000	/* Bank 0 Write Access Time = 1 cycle */
1147
#define B0WAT_2			0x00002000	/* Bank 0 Write Access Time = 2 cycles */
1148
#define B0WAT_3			0x00003000	/* Bank 0 Write Access Time = 3 cycles */
1149
#define B0WAT_4			0x00004000	/* Bank 0 Write Access Time = 4 cycles */
1150
#define B0WAT_5			0x00005000	/* Bank 0 Write Access Time = 5 cycles */
1151
#define B0WAT_6			0x00006000	/* Bank 0 Write Access Time = 6 cycles */
1152
#define B0WAT_7			0x00007000	/* Bank 0 Write Access Time = 7 cycles */
1153
#define B0WAT_8			0x00008000	/* Bank 0 Write Access Time = 8 cycles */
1154
#define B0WAT_9			0x00009000	/* Bank 0 Write Access Time = 9 cycles */
1155
#define B0WAT_10		0x0000A000	/* Bank 0 Write Access Time = 10 cycles */
1156
#define B0WAT_11		0x0000B000	/* Bank 0 Write Access Time = 11 cycles */
1157
#define B0WAT_12		0x0000C000	/* Bank 0 Write Access Time = 12 cycles */
1158
#define B0WAT_13		0x0000D000	/* Bank 0 Write Access Time = 13 cycles */
1159
#define B0WAT_14		0x0000E000	/* Bank 0 Write Access Time = 14 cycles */
1160
#define B0WAT_15		0x0000F000	/* Bank 0 Write Access Time = 15 cycles */
1161
#define B1RDYEN			0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */
1162
#define B1RDYPOL		0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */
1163
#define B1TT_1			0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */
1164
#define B1TT_2			0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */
1165
#define B1TT_3			0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */
1166
#define B1TT_4			0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */
1167
#define B1ST_1			0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1168
#define B1ST_2			0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1169
#define B1ST_3			0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1170
#define B1ST_4			0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1171
#define B1HT_1			0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1172
#define B1HT_2			0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1173
#define B1HT_3			0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1174
#define B1HT_0			0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1175
#define B1RAT_1			0x01000000	/* Bank 1 Read Access Time = 1 cycle */
1176
#define B1RAT_2			0x02000000	/* Bank 1 Read Access Time = 2 cycles */
1177
#define B1RAT_3			0x03000000	/* Bank 1 Read Access Time = 3 cycles */
1178
#define B1RAT_4			0x04000000	/* Bank 1 Read Access Time = 4 cycles */
1179
#define B1RAT_5			0x05000000	/* Bank 1 Read Access Time = 5 cycles */
1180
#define B1RAT_6			0x06000000	/* Bank 1 Read Access Time = 6 cycles */
1181
#define B1RAT_7			0x07000000	/* Bank 1 Read Access Time = 7 cycles */
1182
#define B1RAT_8			0x08000000	/* Bank 1 Read Access Time = 8 cycles */
1183
#define B1RAT_9			0x09000000	/* Bank 1 Read Access Time = 9 cycles */
1184
#define B1RAT_10		0x0A000000	/* Bank 1 Read Access Time = 10 cycles */
1185
#define B1RAT_11		0x0B000000	/* Bank 1 Read Access Time = 11 cycles */
1186
#define B1RAT_12		0x0C000000	/* Bank 1 Read Access Time = 12 cycles */
1187
#define B1RAT_13		0x0D000000	/* Bank 1 Read Access Time = 13 cycles */
1188
#define B1RAT_14		0x0E000000	/* Bank 1 Read Access Time = 14 cycles */
1189
#define B1RAT_15		0x0F000000	/* Bank 1 Read Access Time = 15 cycles */
1190
#define B1WAT_1			0x10000000	/* Bank 1 Write Access Time = 1 cycle */
1191
#define B1WAT_2			0x20000000	/* Bank 1 Write Access Time = 2 cycles */
1192
#define B1WAT_3			0x30000000	/* Bank 1 Write Access Time = 3 cycles */
1193
#define B1WAT_4			0x40000000	/* Bank 1 Write Access Time = 4 cycles */
1194
#define B1WAT_5			0x50000000	/* Bank 1 Write Access Time = 5 cycles */
1195
#define B1WAT_6			0x60000000	/* Bank 1 Write Access Time = 6 cycles */
1196
#define B1WAT_7			0x70000000	/* Bank 1 Write Access Time = 7 cycles */
1197
#define B1WAT_8			0x80000000	/* Bank 1 Write Access Time = 8 cycles */
1198
#define B1WAT_9			0x90000000	/* Bank 1 Write Access Time = 9 cycles */
1199
#define B1WAT_10		0xA0000000	/* Bank 1 Write Access Time = 10 cycles */
1200
#define B1WAT_11		0xB0000000	/* Bank 1 Write Access Time = 11 cycles */
1201
#define B1WAT_12		0xC0000000	/* Bank 1 Write Access Time = 12 cycles */
1202
#define B1WAT_13		0xD0000000	/* Bank 1 Write Access Time = 13 cycles */
1203
#define B1WAT_14		0xE0000000	/* Bank 1 Write Access Time = 14 cycles */
1204
#define B1WAT_15		0xF0000000	/* Bank 1 Write Access Time = 15 cycles */
1205

1206
/* AMBCTL1 Masks */
1207
#define B2RDYEN			0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */
1208
#define B2RDYPOL		0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */
1209
#define B2TT_1			0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */
1210
#define B2TT_2			0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */
1211
#define B2TT_3			0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */
1212
#define B2TT_4			0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */
1213
#define B2ST_1			0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1214
#define B2ST_2			0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1215
#define B2ST_3			0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1216
#define B2ST_4			0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1217
#define B2HT_1			0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1218
#define B2HT_2			0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1219
#define B2HT_3			0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1220
#define B2HT_0			0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1221
#define B2RAT_1			0x00000100	/* Bank 2 Read Access Time = 1 cycle */
1222
#define B2RAT_2			0x00000200	/* Bank 2 Read Access Time = 2 cycles */
1223
#define B2RAT_3			0x00000300	/* Bank 2 Read Access Time = 3 cycles */
1224
#define B2RAT_4			0x00000400	/* Bank 2 Read Access Time = 4 cycles */
1225
#define B2RAT_5			0x00000500	/* Bank 2 Read Access Time = 5 cycles */
1226
#define B2RAT_6			0x00000600	/* Bank 2 Read Access Time = 6 cycles */
1227
#define B2RAT_7			0x00000700	/* Bank 2 Read Access Time = 7 cycles */
1228
#define B2RAT_8			0x00000800	/* Bank 2 Read Access Time = 8 cycles */
1229
#define B2RAT_9			0x00000900	/* Bank 2 Read Access Time = 9 cycles */
1230
#define B2RAT_10		0x00000A00	/* Bank 2 Read Access Time = 10 cycles */
1231
#define B2RAT_11		0x00000B00	/* Bank 2 Read Access Time = 11 cycles */
1232
#define B2RAT_12		0x00000C00	/* Bank 2 Read Access Time = 12 cycles */
1233
#define B2RAT_13		0x00000D00	/* Bank 2 Read Access Time = 13 cycles */
1234
#define B2RAT_14		0x00000E00	/* Bank 2 Read Access Time = 14 cycles */
1235
#define B2RAT_15		0x00000F00	/* Bank 2 Read Access Time = 15 cycles */
1236
#define B2WAT_1			0x00001000	/* Bank 2 Write Access Time = 1 cycle */
1237
#define B2WAT_2			0x00002000	/* Bank 2 Write Access Time = 2 cycles */
1238
#define B2WAT_3			0x00003000	/* Bank 2 Write Access Time = 3 cycles */
1239
#define B2WAT_4			0x00004000	/* Bank 2 Write Access Time = 4 cycles */
1240
#define B2WAT_5			0x00005000	/* Bank 2 Write Access Time = 5 cycles */
1241
#define B2WAT_6			0x00006000	/* Bank 2 Write Access Time = 6 cycles */
1242
#define B2WAT_7			0x00007000	/* Bank 2 Write Access Time = 7 cycles */
1243
#define B2WAT_8			0x00008000	/* Bank 2 Write Access Time = 8 cycles */
1244
#define B2WAT_9			0x00009000	/* Bank 2 Write Access Time = 9 cycles */
1245
#define B2WAT_10		0x0000A000	/* Bank 2 Write Access Time = 10 cycles */
1246
#define B2WAT_11		0x0000B000	/* Bank 2 Write Access Time = 11 cycles */
1247
#define B2WAT_12		0x0000C000	/* Bank 2 Write Access Time = 12 cycles */
1248
#define B2WAT_13		0x0000D000	/* Bank 2 Write Access Time = 13 cycles */
1249
#define B2WAT_14		0x0000E000	/* Bank 2 Write Access Time = 14 cycles */
1250
#define B2WAT_15		0x0000F000	/* Bank 2 Write Access Time = 15 cycles */
1251
#define B3RDYEN			0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */
1252
#define B3RDYPOL		0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */
1253
#define B3TT_1			0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */
1254
#define B3TT_2			0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */
1255
#define B3TT_3			0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */
1256
#define B3TT_4			0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */
1257
#define B3ST_1			0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1258
#define B3ST_2			0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1259
#define B3ST_3			0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1260
#define B3ST_4			0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1261
#define B3HT_1			0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1262
#define B3HT_2			0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1263
#define B3HT_3			0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1264
#define B3HT_0			0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1265
#define B3RAT_1			0x01000000	/* Bank 3 Read Access Time = 1 cycle */
1266
#define B3RAT_2			0x02000000	/* Bank 3 Read Access Time = 2 cycles */
1267
#define B3RAT_3			0x03000000	/* Bank 3 Read Access Time = 3 cycles */
1268
#define B3RAT_4			0x04000000	/* Bank 3 Read Access Time = 4 cycles */
1269
#define B3RAT_5			0x05000000	/* Bank 3 Read Access Time = 5 cycles */
1270
#define B3RAT_6			0x06000000	/* Bank 3 Read Access Time = 6 cycles */
1271
#define B3RAT_7			0x07000000	/* Bank 3 Read Access Time = 7 cycles */
1272
#define B3RAT_8			0x08000000	/* Bank 3 Read Access Time = 8 cycles */
1273
#define B3RAT_9			0x09000000	/* Bank 3 Read Access Time = 9 cycles */
1274
#define B3RAT_10		0x0A000000	/* Bank 3 Read Access Time = 10 cycles */
1275
#define B3RAT_11		0x0B000000	/* Bank 3 Read Access Time = 11 cycles */
1276
#define B3RAT_12		0x0C000000	/* Bank 3 Read Access Time = 12 cycles */
1277
#define B3RAT_13		0x0D000000	/* Bank 3 Read Access Time = 13 cycles */
1278
#define B3RAT_14		0x0E000000	/* Bank 3 Read Access Time = 14 cycles */
1279
#define B3RAT_15		0x0F000000	/* Bank 3 Read Access Time = 15 cycles */
1280
#define B3WAT_1			0x10000000	/* Bank 3 Write Access Time = 1 cycle */
1281
#define B3WAT_2			0x20000000	/* Bank 3 Write Access Time = 2 cycles */
1282
#define B3WAT_3			0x30000000	/* Bank 3 Write Access Time = 3 cycles */
1283
#define B3WAT_4			0x40000000	/* Bank 3 Write Access Time = 4 cycles */
1284
#define B3WAT_5			0x50000000	/* Bank 3 Write Access Time = 5 cycles */
1285
#define B3WAT_6			0x60000000	/* Bank 3 Write Access Time = 6 cycles */
1286
#define B3WAT_7			0x70000000	/* Bank 3 Write Access Time = 7 cycles */
1287
#define B3WAT_8			0x80000000	/* Bank 3 Write Access Time = 8 cycles */
1288
#define B3WAT_9			0x90000000	/* Bank 3 Write Access Time = 9 cycles */
1289
#define B3WAT_10		0xA0000000	/* Bank 3 Write Access Time = 10 cycles */
1290
#define B3WAT_11		0xB0000000	/* Bank 3 Write Access Time = 11 cycles */
1291
#define B3WAT_12		0xC0000000	/* Bank 3 Write Access Time = 12 cycles */
1292
#define B3WAT_13		0xD0000000	/* Bank 3 Write Access Time = 13 cycles */
1293
#define B3WAT_14		0xE0000000	/* Bank 3 Write Access Time = 14 cycles */
1294
#define B3WAT_15		0xF0000000	/* Bank 3 Write Access Time = 15 cycles */
1295

1296
/* **********************  SDRAM CONTROLLER MASKS  *************************** */
1297

1298
/* EBIU_SDGCTL Masks */
1299
#define SCTLE			0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1300
#define CL_2			0x00000008	/* SDRAM CAS latency = 2 cycles */
1301
#define CL_3			0x0000000C	/* SDRAM CAS latency = 3 cycles */
1302
#define PFE			0x00000010	/* Enable SDRAM prefetch */
1303
#define PFP			0x00000020	/* Prefetch has priority over AMC requests */
1304
#define TRAS_1			0x00000040	/* SDRAM tRAS = 1 cycle */
1305
#define TRAS_2			0x00000080	/* SDRAM tRAS = 2 cycles */
1306
#define TRAS_3			0x000000C0	/* SDRAM tRAS = 3 cycles */
1307
#define TRAS_4			0x00000100	/* SDRAM tRAS = 4 cycles */
1308
#define TRAS_5			0x00000140	/* SDRAM tRAS = 5 cycles */
1309
#define TRAS_6			0x00000180	/* SDRAM tRAS = 6 cycles */
1310
#define TRAS_7			0x000001C0	/* SDRAM tRAS = 7 cycles */
1311
#define TRAS_8			0x00000200	/* SDRAM tRAS = 8 cycles */
1312
#define TRAS_9			0x00000240	/* SDRAM tRAS = 9 cycles */
1313
#define TRAS_10			0x00000280	/* SDRAM tRAS = 10 cycles */
1314
#define TRAS_11			0x000002C0	/* SDRAM tRAS = 11 cycles */
1315
#define TRAS_12			0x00000300	/* SDRAM tRAS = 12 cycles */
1316
#define TRAS_13			0x00000340	/* SDRAM tRAS = 13 cycles */
1317
#define TRAS_14			0x00000380	/* SDRAM tRAS = 14 cycles */
1318
#define TRAS_15			0x000003C0	/* SDRAM tRAS = 15 cycles */
1319
#define TRP_1			0x00000800	/* SDRAM tRP = 1 cycle */
1320
#define TRP_2			0x00001000	/* SDRAM tRP = 2 cycles */
1321
#define TRP_3			0x00001800	/* SDRAM tRP = 3 cycles */
1322
#define TRP_4			0x00002000	/* SDRAM tRP = 4 cycles */
1323
#define TRP_5			0x00002800	/* SDRAM tRP = 5 cycles */
1324
#define TRP_6			0x00003000	/* SDRAM tRP = 6 cycles */
1325
#define TRP_7			0x00003800	/* SDRAM tRP = 7 cycles */
1326
#define TRCD_1			0x00008000	/* SDRAM tRCD = 1 cycle */
1327
#define TRCD_2			0x00010000	/* SDRAM tRCD = 2 cycles */
1328
#define TRCD_3			0x00018000	/* SDRAM tRCD = 3 cycles */
1329
#define TRCD_4			0x00020000	/* SDRAM tRCD = 4 cycles */
1330
#define TRCD_5			0x00028000	/* SDRAM tRCD = 5 cycles */
1331
#define TRCD_6			0x00030000	/* SDRAM tRCD = 6 cycles */
1332
#define TRCD_7			0x00038000	/* SDRAM tRCD = 7 cycles */
1333
#define TWR_1			0x00080000	/* SDRAM tWR = 1 cycle */
1334
#define TWR_2			0x00100000	/* SDRAM tWR = 2 cycles */
1335
#define TWR_3			0x00180000	/* SDRAM tWR = 3 cycles */
1336
#define PUPSD			0x00200000	/*Power-up start delay */
1337
#define PSM			0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1338
#define PSS				0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */
1339
#define SRFS			0x01000000	/* Start SDRAM self-refresh mode */
1340
#define EBUFE			0x02000000	/* Enable external buffering timing */
1341
#define FBBRW			0x04000000	/* Fast back-to-back read write enable */
1342
#define EMREN			0x10000000	/* Extended mode register enable */
1343
#define TCSR			0x20000000	/* Temp compensated self refresh value 85 deg C */
1344
#define CDDBG			0x40000000	/* Tristate SDRAM controls during bus grant */
1345

1346
/* EBIU_SDBCTL Masks */
1347
#define EB0_E				0x00000001	/* Enable SDRAM external bank 0 */
1348
#define EB0_SZ_16			0x00000000	/* SDRAM external bank size = 16MB */
1349
#define EB0_SZ_32			0x00000002	/* SDRAM external bank size = 32MB */
1350
#define EB0_SZ_64			0x00000004	/* SDRAM external bank size = 64MB */
1351
#define EB0_SZ_128			0x00000006	/* SDRAM external bank size = 128MB */
1352
#define EB0_CAW_8			0x00000000	/* SDRAM external bank column address width = 8 bits */
1353
#define EB0_CAW_9			0x00000010	/* SDRAM external bank column address width = 9 bits */
1354
#define EB0_CAW_10			0x00000020	/* SDRAM external bank column address width = 9 bits */
1355
#define EB0_CAW_11			0x00000030	/* SDRAM external bank column address width = 9 bits */
1356

1357
#define EB1_E				0x00000100	/* Enable SDRAM external bank 1 */
1358
#define EB1__SZ_16			0x00000000	/* SDRAM external bank size = 16MB */
1359
#define EB1__SZ_32			0x00000200	/* SDRAM external bank size = 32MB */
1360
#define EB1__SZ_64			0x00000400	/* SDRAM external bank size = 64MB */
1361
#define EB1__SZ_128			0x00000600	/* SDRAM external bank size = 128MB */
1362
#define EB1__CAW_8			0x00000000	/* SDRAM external bank column address width = 8 bits */
1363
#define EB1__CAW_9			0x00001000	/* SDRAM external bank column address width = 9 bits */
1364
#define EB1__CAW_10			0x00002000	/* SDRAM external bank column address width = 9 bits */
1365
#define EB1__CAW_11			0x00003000	/* SDRAM external bank column address width = 9 bits */
1366

1367
#define EB2__E				0x00010000	/* Enable SDRAM external bank 2 */
1368
#define EB2__SZ_16			0x00000000	/* SDRAM external bank size = 16MB */
1369
#define EB2__SZ_32			0x00020000	/* SDRAM external bank size = 32MB */
1370
#define EB2__SZ_64			0x00040000	/* SDRAM external bank size = 64MB */
1371
#define EB2__SZ_128			0x00060000	/* SDRAM external bank size = 128MB */
1372
#define EB2__CAW_8			0x00000000	/* SDRAM external bank column address width = 8 bits */
1373
#define EB2__CAW_9			0x00100000	/* SDRAM external bank column address width = 9 bits */
1374
#define EB2__CAW_10			0x00200000	/* SDRAM external bank column address width = 9 bits */
1375
#define EB2__CAW_11			0x00300000	/* SDRAM external bank column address width = 9 bits */
1376

1377
#define EB3__E				0x01000000	/* Enable SDRAM external bank 3 */
1378
#define EB3__SZ_16			0x00000000	/* SDRAM external bank size = 16MB */
1379
#define EB3__SZ_32			0x02000000	/* SDRAM external bank size = 32MB */
1380
#define EB3__SZ_64			0x04000000	/* SDRAM external bank size = 64MB */
1381
#define EB3__SZ_128			0x06000000	/* SDRAM external bank size = 128MB */
1382
#define EB3__CAW_8			0x00000000	/* SDRAM external bank column address width = 8 bits */
1383
#define EB3__CAW_9			0x10000000	/* SDRAM external bank column address width = 9 bits */
1384
#define EB3__CAW_10			0x20000000	/* SDRAM external bank column address width = 9 bits */
1385
#define EB3__CAW_11			0x30000000	/* SDRAM external bank column address width = 9 bits */
1386

1387
/* EBIU_SDSTAT Masks */
1388
#define SDCI			0x00000001	/* SDRAM controller is idle  */
1389
#define SDSRA			0x00000002	/* SDRAM SDRAM self refresh is active */
1390
#define SDPUA			0x00000004	/* SDRAM power up active  */
1391
#define SDRS			0x00000008	/* SDRAM is in reset state */
1392
#define SDEASE		    0x00000010	/* SDRAM EAB sticky error status - W1C */
1393
#define BGSTAT			0x00000020	/* Bus granted */
1394

1395
#endif				/* _DEF_BF561_H */
1396

1397
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