Path: blob/master/arch/blackfin/mach-bf561/include/mach/portmux.h
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/*1* Copyright 2007-2009 Analog Devices Inc.2*3* Licensed under the GPL-2 or later.4*/56#ifndef _MACH_PORTMUX_H_7#define _MACH_PORTMUX_H_89#define MAX_RESOURCES MAX_BLACKFIN_GPIOS1011#define P_PPI0_CLK (P_DONTCARE)12#define P_PPI0_FS1 (P_DONTCARE)13#define P_PPI0_FS2 (P_DONTCARE)14#define P_PPI0_FS3 (P_DONTCARE)15#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))16#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))17#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))18#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))19#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))20#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))21#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))22#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))23#define P_PPI0_D0 (P_DONTCARE)24#define P_PPI0_D1 (P_DONTCARE)25#define P_PPI0_D2 (P_DONTCARE)26#define P_PPI0_D3 (P_DONTCARE)27#define P_PPI0_D4 (P_DONTCARE)28#define P_PPI0_D5 (P_DONTCARE)29#define P_PPI0_D6 (P_DONTCARE)30#define P_PPI0_D7 (P_DONTCARE)31#define P_PPI1_CLK (P_DONTCARE)32#define P_PPI1_FS1 (P_DONTCARE)33#define P_PPI1_FS2 (P_DONTCARE)34#define P_PPI1_FS3 (P_DONTCARE)35#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))36#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))37#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))38#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))39#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))40#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))41#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))42#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))43#define P_PPI1_D0 (P_DONTCARE)44#define P_PPI1_D1 (P_DONTCARE)45#define P_PPI1_D2 (P_DONTCARE)46#define P_PPI1_D3 (P_DONTCARE)47#define P_PPI1_D4 (P_DONTCARE)48#define P_PPI1_D5 (P_DONTCARE)49#define P_PPI1_D6 (P_DONTCARE)50#define P_PPI1_D7 (P_DONTCARE)51#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))52#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))53#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))54#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))55#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))56#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))57#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))58#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))59#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))60#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))61#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))62#define P_SPORT1_DRPRI (P_DONTCARE)63#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))64#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))65#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))66#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))67#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))68#define P_SPORT0_DRPRI (P_DONTCARE)69#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))70#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))71#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))72#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))73#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))74#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))75#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))76#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))77#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))78#define P_TMR11 (P_DONTCARE)79#define P_TMR10 (P_DONTCARE)80#define P_TMR9 (P_DONTCARE)81#define P_TMR8 (P_DONTCARE)82#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))83#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))84#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))85#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))86#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))87#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))88#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))89#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))90#define P_SPI0_MOSI (P_DONTCARE)91#define P_SPI0_MISO (P_DONTCARE)92#define P_SPI0_SCK (P_DONTCARE)93#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF294#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL29596#endif /* _MACH_PORTMUX_H_ */979899