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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/blackfin/mach-common/cache.S
10817 views
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/*

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 * Blackfin cache control code

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 *

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 * Copyright 2004-2008 Analog Devices Inc.

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 *

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 * Licensed under the GPL-2 or later.

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 */

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#include <linux/linkage.h>

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#include <asm/blackfin.h>

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#include <asm/cache.h>

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#include <asm/page.h>

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/* 05000443 - IFLUSH cannot be last instruction in hardware loop */

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#if ANOMALY_05000443

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# define BROK_FLUSH_INST "IFLUSH"

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#else

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# define BROK_FLUSH_INST "no anomaly! yeah!"

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#endif

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/* Since all L1 caches work the same way, we use the same method for flushing

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 * them.  Only the actual flush instruction differs.  We write this in asm as

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 * GCC can be hard to coax into writing nice hardware loops.

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 *

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 * Also, we assume the following register setup:

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 * R0 = start address

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 * R1 = end address

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 */

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.macro do_flush flushins:req label

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	R2 = -L1_CACHE_BYTES;

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	/* start = (start & -L1_CACHE_BYTES) */

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	R0 = R0 & R2;

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	/* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */

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	R1 += -1;

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	R1 = R1 & R2;

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	R1 += L1_CACHE_BYTES;

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	/* count = (end - start) >> L1_CACHE_SHIFT */

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	R2 = R1 - R0;

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	R2 >>= L1_CACHE_SHIFT;

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	P1 = R2;

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.ifnb \label

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\label :

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.endif

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	P0 = R0;

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	LSETUP (1f, 2f) LC1 = P1;

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1:

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.ifeqs "\flushins", BROK_FLUSH_INST

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	\flushins [P0++];

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	nop;

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	nop;

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2:	nop;

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.else

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2:	\flushins [P0++];

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.endif

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	RTS;

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.endm

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#ifdef CONFIG_ICACHE_FLUSH_L1

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.section .l1.text

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#else

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.text

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#endif

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/* Invalidate all instruction cache lines assocoiated with this memory area */

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#ifdef CONFIG_SMP

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# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1

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#endif

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ENTRY(_blackfin_icache_flush_range)

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	do_flush IFLUSH

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ENDPROC(_blackfin_icache_flush_range)

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#ifdef CONFIG_SMP

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.text

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# undef _blackfin_icache_flush_range

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ENTRY(_blackfin_icache_flush_range)

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	p0.L = LO(DSPID);

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	p0.H = HI(DSPID);

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	r3 = [p0];

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	r3 = r3.b (z);

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	p2 = r3;

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	p0.L = _blackfin_iflush_l1_entry;

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	p0.H = _blackfin_iflush_l1_entry;

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	p0 = p0 + (p2 << 2);

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	p1 = [p0];

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	jump (p1);

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ENDPROC(_blackfin_icache_flush_range)

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#endif

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#ifdef CONFIG_DCACHE_FLUSH_L1

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.section .l1.text

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#else

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.text

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#endif

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/* Throw away all D-cached data in specified region without any obligation to

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 * write them back.  Since the Blackfin ISA does not have an "invalidate"

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 * instruction, we use flush/invalidate.  Perhaps as a speed optimization we

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 * could bang on the DTEST MMRs ...

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 */

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ENTRY(_blackfin_dcache_invalidate_range)

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	do_flush FLUSHINV

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ENDPROC(_blackfin_dcache_invalidate_range)

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/* Flush all data cache lines assocoiated with this memory area */

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ENTRY(_blackfin_dcache_flush_range)

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	do_flush FLUSH, .Ldfr

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ENDPROC(_blackfin_dcache_flush_range)

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/* Our headers convert the page structure to an address, so just need to flush

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 * its contents like normal.  We know the start address is page aligned (which

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 * greater than our cache alignment), as is the end address.  So just jump into

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 * the middle of the dcache flush function.

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 */

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ENTRY(_blackfin_dflush_page)

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	P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);

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	jump .Ldfr;

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ENDPROC(_blackfin_dflush_page)

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