CoCalc -- dpmc

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/blackfin/mach-common/dpmc_modes.S
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/*
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 * Copyright 2004-2008 Analog Devices Inc.
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 *
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 * Licensed under the GPL-2 or later.
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 */
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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#include <mach/irq.h>
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#include <asm/dpmc.h>
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.section .l1.text
13

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ENTRY(_sleep_mode)
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	[--SP] = ( R7:0, P5:0 );
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	[--SP] =  RETS;
17

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	call _set_sic_iwr;
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	P0.H = hi(PLL_CTL);
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	P0.L = lo(PLL_CTL);
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	R1 = W[P0](z);
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	BITSET (R1, 3);
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	W[P0] = R1.L;
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	CLI R2;
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	SSYNC;
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	IDLE;
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	STI R2;
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	call _test_pll_locked;
32

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	R0 = IWR_ENABLE(0);
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	R1 = IWR_DISABLE_ALL;
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	R2 = IWR_DISABLE_ALL;
36

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	call _set_sic_iwr;
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	P0.H = hi(PLL_CTL);
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	P0.L = lo(PLL_CTL);
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	R7 = w[p0](z);
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	BITCLR (R7, 3);
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	BITCLR (R7, 5);
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	w[p0] = R7.L;
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	IDLE;
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	call _test_pll_locked;
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	RETS = [SP++];
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	( R7:0, P5:0 ) = [SP++];
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	RTS;
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ENDPROC(_sleep_mode)
52

53
ENTRY(_hibernate_mode)
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	[--SP] = ( R7:0, P5:0 );
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	[--SP] =  RETS;
56

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	R3 = R0;
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	R0 = IWR_DISABLE_ALL;
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	R1 = IWR_DISABLE_ALL;
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	R2 = IWR_DISABLE_ALL;
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	call _set_sic_iwr;
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	call _set_dram_srfs;
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	SSYNC;
64

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	P0.H = hi(VR_CTL);
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	P0.L = lo(VR_CTL);
67

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	W[P0] = R3.L;
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	CLI R2;
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	IDLE;
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.Lforever:
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	jump .Lforever;
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ENDPROC(_hibernate_mode)
74

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ENTRY(_sleep_deeper)
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	[--SP] = ( R7:0, P5:0 );
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	[--SP] =  RETS;
78

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	CLI R4;
80

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	P3 = R0;
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	P4 = R1;
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	P5 = R2;
84

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	R0 = IWR_ENABLE(0);
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	R1 = IWR_DISABLE_ALL;
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	R2 = IWR_DISABLE_ALL;
88

89
	call _set_sic_iwr;
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	call _set_dram_srfs;	/* Set SDRAM Self Refresh */
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	P0.H = hi(PLL_DIV);
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	P0.L = lo(PLL_DIV);
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	R6 = W[P0](z);
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	R0.L = 0xF;
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	W[P0] = R0.l;		/* Set Max VCO to SCLK divider */
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	P0.H = hi(PLL_CTL);
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	P0.L = lo(PLL_CTL);
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	R5 = W[P0](z);
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	R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
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	W[P0] = R0.l;		/* Set Min CLKIN to VCO multiplier */
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	SSYNC;
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	IDLE;
106

107
	call _test_pll_locked;
108

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	P0.H = hi(VR_CTL);
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	P0.L = lo(VR_CTL);
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	R7 = W[P0](z);
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	R1 = 0x6;
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	R1 <<= 16;
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	R2 = 0x0404(Z);
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	R1 = R1|R2;
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	R2 = DEPOSIT(R7, R1);
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	W[P0] = R2;		/* Set Min Core Voltage */
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120
	SSYNC;
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	IDLE;
122

123
	call _test_pll_locked;
124

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	R0 = P3;
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	R1 = P4;
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	R3 = P5;
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	call _set_sic_iwr;	/* Set Awake from IDLE */
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	P0.H = hi(PLL_CTL);
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	P0.L = lo(PLL_CTL);
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	R0 = W[P0](z);
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	BITSET (R0, 3);
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	W[P0] = R0.L;		/* Turn CCLK OFF */
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	SSYNC;
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	IDLE;
137

138
	call _test_pll_locked;
139

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	R0 = IWR_ENABLE(0);
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	R1 = IWR_DISABLE_ALL;
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	R2 = IWR_DISABLE_ALL;
143

144
	call _set_sic_iwr;	/* Set Awake from IDLE PLL */
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	P0.H = hi(VR_CTL);
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	P0.L = lo(VR_CTL);
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	W[P0]= R7;
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150
	SSYNC;
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	IDLE;
152

153
	call _test_pll_locked;
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	P0.H = hi(PLL_DIV);
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	P0.L = lo(PLL_DIV);
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	W[P0]= R6;		/* Restore CCLK and SCLK divider */
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	P0.H = hi(PLL_CTL);
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	P0.L = lo(PLL_CTL);
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	w[p0] = R5;		/* Restore VCO multiplier */
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	IDLE;
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	call _test_pll_locked;
164

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	call _unset_dram_srfs;	/* SDRAM Self Refresh Off */
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167
	STI R4;
168

169
	RETS = [SP++];
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	( R7:0, P5:0 ) = [SP++];
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	RTS;
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ENDPROC(_sleep_deeper)
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174
ENTRY(_set_dram_srfs)
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	/*  set the dram to self refresh mode */
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	SSYNC;
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#if defined(EBIU_RSTCTL)	/* DDR */
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	P0.H = hi(EBIU_RSTCTL);
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	P0.L = lo(EBIU_RSTCTL);
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	R2 = [P0];
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	BITSET(R2, 3); /* SRREQ enter self-refresh mode */
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	[P0] = R2;
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	SSYNC;
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1:
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	R2 = [P0];
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	CC = BITTST(R2, 4);
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	if !CC JUMP 1b;
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#else 				/* SDRAM */
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	P0.L = lo(EBIU_SDGCTL);
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	P0.H = hi(EBIU_SDGCTL);
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	R2 = [P0];
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	BITSET(R2, 24); /* SRFS enter self-refresh mode */
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	[P0] = R2;
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	SSYNC;
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	P0.L = lo(EBIU_SDSTAT);
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	P0.H = hi(EBIU_SDSTAT);
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1:
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	R2 = w[P0];
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	SSYNC;
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	cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
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	if !cc jump 1b;
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	P0.L = lo(EBIU_SDGCTL);
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	P0.H = hi(EBIU_SDGCTL);
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	R2 = [P0];
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	BITCLR(R2, 0); /* SCTLE disable CLKOUT */
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	[P0] = R2;
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#endif
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	RTS;
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ENDPROC(_set_dram_srfs)
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ENTRY(_unset_dram_srfs)
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	/*  set the dram out of self refresh mode */
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#if defined(EBIU_RSTCTL)	/* DDR */
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	P0.H = hi(EBIU_RSTCTL);
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	P0.L = lo(EBIU_RSTCTL);
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	R2 = [P0];
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	BITCLR(R2, 3); /* clear SRREQ bit */
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	[P0] = R2;
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#elif defined(EBIU_SDGCTL)	/* SDRAM */
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	P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
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	P0.H = hi(EBIU_SDGCTL);
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	R2 = [P0];
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	BITSET(R2, 0); /* SCTLE enable CLKOUT */
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	[P0] = R2
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	SSYNC;
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	P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
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	P0.H = hi(EBIU_SDGCTL);
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	R2 = [P0];
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	BITCLR(R2, 24); /* clear SRFS bit */
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	[P0] = R2
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#endif
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	SSYNC;
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	RTS;
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ENDPROC(_unset_dram_srfs)
239

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ENTRY(_set_sic_iwr)
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
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	defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
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	P0.H = hi(SIC_IWR0);
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	P0.L = lo(SIC_IWR0);
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	P1.H = hi(SIC_IWR1);
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	P1.L = lo(SIC_IWR1);
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	[P1] = R1;
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#if defined(CONFIG_BF54x)
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	P1.H = hi(SIC_IWR2);
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	P1.L = lo(SIC_IWR2);
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	[P1] = R2;
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#endif
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#else
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	P0.H = hi(SIC_IWR);
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	P0.L = lo(SIC_IWR);
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#endif
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	[P0] = R0;
258

259
	SSYNC;
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	RTS;
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ENDPROC(_set_sic_iwr)
262

263
ENTRY(_test_pll_locked)
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	P0.H = hi(PLL_STAT);
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	P0.L = lo(PLL_STAT);
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1:
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	R0 = W[P0] (Z);
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	CC = BITTST(R0,5);
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	IF !CC JUMP 1b;
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	RTS;
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ENDPROC(_test_pll_locked)
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.section .text
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ENTRY(_do_hibernate)
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	[--SP] = ( R7:0, P5:0 );
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	[--SP] =  RETS;
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	/* Save System MMRs */
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	R2 = R0;
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	P0.H = hi(PLL_CTL);
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	P0.L = lo(PLL_CTL);
282

283
#ifdef SIC_IMASK0
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	PM_SYS_PUSH(SIC_IMASK0)
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#endif
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#ifdef SIC_IMASK1
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	PM_SYS_PUSH(SIC_IMASK1)
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#endif
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#ifdef SIC_IMASK2
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	PM_SYS_PUSH(SIC_IMASK2)
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#endif
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#ifdef SIC_IMASK
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	PM_SYS_PUSH(SIC_IMASK)
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#endif
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#ifdef SIC_IAR0
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	PM_SYS_PUSH(SIC_IAR0)
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	PM_SYS_PUSH(SIC_IAR1)
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	PM_SYS_PUSH(SIC_IAR2)
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#endif
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#ifdef SIC_IAR3
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	PM_SYS_PUSH(SIC_IAR3)
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#endif
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#ifdef SIC_IAR4
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	PM_SYS_PUSH(SIC_IAR4)
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	PM_SYS_PUSH(SIC_IAR5)
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	PM_SYS_PUSH(SIC_IAR6)
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#endif
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#ifdef SIC_IAR7
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	PM_SYS_PUSH(SIC_IAR7)
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#endif
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#ifdef SIC_IAR8
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	PM_SYS_PUSH(SIC_IAR8)
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	PM_SYS_PUSH(SIC_IAR9)
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	PM_SYS_PUSH(SIC_IAR10)
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	PM_SYS_PUSH(SIC_IAR11)
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#endif
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#ifdef SIC_IWR
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	PM_SYS_PUSH(SIC_IWR)
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#endif
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#ifdef SIC_IWR0
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	PM_SYS_PUSH(SIC_IWR0)
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#endif
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#ifdef SIC_IWR1
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	PM_SYS_PUSH(SIC_IWR1)
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#endif
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#ifdef SIC_IWR2
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	PM_SYS_PUSH(SIC_IWR2)
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#endif
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#ifdef PINT0_ASSIGN
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	PM_SYS_PUSH(PINT0_MASK_SET)
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	PM_SYS_PUSH(PINT1_MASK_SET)
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	PM_SYS_PUSH(PINT2_MASK_SET)
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	PM_SYS_PUSH(PINT3_MASK_SET)
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	PM_SYS_PUSH(PINT0_ASSIGN)
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	PM_SYS_PUSH(PINT1_ASSIGN)
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	PM_SYS_PUSH(PINT2_ASSIGN)
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	PM_SYS_PUSH(PINT3_ASSIGN)
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	PM_SYS_PUSH(PINT0_INVERT_SET)
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	PM_SYS_PUSH(PINT1_INVERT_SET)
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	PM_SYS_PUSH(PINT2_INVERT_SET)
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	PM_SYS_PUSH(PINT3_INVERT_SET)
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	PM_SYS_PUSH(PINT0_EDGE_SET)
345
	PM_SYS_PUSH(PINT1_EDGE_SET)
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	PM_SYS_PUSH(PINT2_EDGE_SET)
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	PM_SYS_PUSH(PINT3_EDGE_SET)
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#endif
349

350
	PM_SYS_PUSH(EBIU_AMBCTL0)
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	PM_SYS_PUSH(EBIU_AMBCTL1)
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	PM_SYS_PUSH16(EBIU_AMGCTL)
353

354
#ifdef EBIU_FCTL
355
	PM_SYS_PUSH(EBIU_MBSCTL)
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	PM_SYS_PUSH(EBIU_MODE)
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	PM_SYS_PUSH(EBIU_FCTL)
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#endif
359

360
#ifdef PORTCIO_FER
361
	PM_SYS_PUSH16(PORTCIO_DIR)
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	PM_SYS_PUSH16(PORTCIO_INEN)
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	PM_SYS_PUSH16(PORTCIO)
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	PM_SYS_PUSH16(PORTCIO_FER)
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	PM_SYS_PUSH16(PORTDIO_DIR)
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	PM_SYS_PUSH16(PORTDIO_INEN)
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	PM_SYS_PUSH16(PORTDIO)
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	PM_SYS_PUSH16(PORTDIO_FER)
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	PM_SYS_PUSH16(PORTEIO_DIR)
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	PM_SYS_PUSH16(PORTEIO_INEN)
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	PM_SYS_PUSH16(PORTEIO)
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	PM_SYS_PUSH16(PORTEIO_FER)
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#endif
374

375
	PM_SYS_PUSH16(SYSCR)
376

377
	/* Save Core MMRs */
378
	P0.H = hi(SRAM_BASE_ADDRESS);
379
	P0.L = lo(SRAM_BASE_ADDRESS);
380

381
	PM_PUSH(DMEM_CONTROL)
382
	PM_PUSH(DCPLB_ADDR0)
383
	PM_PUSH(DCPLB_ADDR1)
384
	PM_PUSH(DCPLB_ADDR2)
385
	PM_PUSH(DCPLB_ADDR3)
386
	PM_PUSH(DCPLB_ADDR4)
387
	PM_PUSH(DCPLB_ADDR5)
388
	PM_PUSH(DCPLB_ADDR6)
389
	PM_PUSH(DCPLB_ADDR7)
390
	PM_PUSH(DCPLB_ADDR8)
391
	PM_PUSH(DCPLB_ADDR9)
392
	PM_PUSH(DCPLB_ADDR10)
393
	PM_PUSH(DCPLB_ADDR11)
394
	PM_PUSH(DCPLB_ADDR12)
395
	PM_PUSH(DCPLB_ADDR13)
396
	PM_PUSH(DCPLB_ADDR14)
397
	PM_PUSH(DCPLB_ADDR15)
398
	PM_PUSH(DCPLB_DATA0)
399
	PM_PUSH(DCPLB_DATA1)
400
	PM_PUSH(DCPLB_DATA2)
401
	PM_PUSH(DCPLB_DATA3)
402
	PM_PUSH(DCPLB_DATA4)
403
	PM_PUSH(DCPLB_DATA5)
404
	PM_PUSH(DCPLB_DATA6)
405
	PM_PUSH(DCPLB_DATA7)
406
	PM_PUSH(DCPLB_DATA8)
407
	PM_PUSH(DCPLB_DATA9)
408
	PM_PUSH(DCPLB_DATA10)
409
	PM_PUSH(DCPLB_DATA11)
410
	PM_PUSH(DCPLB_DATA12)
411
	PM_PUSH(DCPLB_DATA13)
412
	PM_PUSH(DCPLB_DATA14)
413
	PM_PUSH(DCPLB_DATA15)
414
	PM_PUSH(IMEM_CONTROL)
415
	PM_PUSH(ICPLB_ADDR0)
416
	PM_PUSH(ICPLB_ADDR1)
417
	PM_PUSH(ICPLB_ADDR2)
418
	PM_PUSH(ICPLB_ADDR3)
419
	PM_PUSH(ICPLB_ADDR4)
420
	PM_PUSH(ICPLB_ADDR5)
421
	PM_PUSH(ICPLB_ADDR6)
422
	PM_PUSH(ICPLB_ADDR7)
423
	PM_PUSH(ICPLB_ADDR8)
424
	PM_PUSH(ICPLB_ADDR9)
425
	PM_PUSH(ICPLB_ADDR10)
426
	PM_PUSH(ICPLB_ADDR11)
427
	PM_PUSH(ICPLB_ADDR12)
428
	PM_PUSH(ICPLB_ADDR13)
429
	PM_PUSH(ICPLB_ADDR14)
430
	PM_PUSH(ICPLB_ADDR15)
431
	PM_PUSH(ICPLB_DATA0)
432
	PM_PUSH(ICPLB_DATA1)
433
	PM_PUSH(ICPLB_DATA2)
434
	PM_PUSH(ICPLB_DATA3)
435
	PM_PUSH(ICPLB_DATA4)
436
	PM_PUSH(ICPLB_DATA5)
437
	PM_PUSH(ICPLB_DATA6)
438
	PM_PUSH(ICPLB_DATA7)
439
	PM_PUSH(ICPLB_DATA8)
440
	PM_PUSH(ICPLB_DATA9)
441
	PM_PUSH(ICPLB_DATA10)
442
	PM_PUSH(ICPLB_DATA11)
443
	PM_PUSH(ICPLB_DATA12)
444
	PM_PUSH(ICPLB_DATA13)
445
	PM_PUSH(ICPLB_DATA14)
446
	PM_PUSH(ICPLB_DATA15)
447
	PM_PUSH(EVT0)
448
	PM_PUSH(EVT1)
449
	PM_PUSH(EVT2)
450
	PM_PUSH(EVT3)
451
	PM_PUSH(EVT4)
452
	PM_PUSH(EVT5)
453
	PM_PUSH(EVT6)
454
	PM_PUSH(EVT7)
455
	PM_PUSH(EVT8)
456
	PM_PUSH(EVT9)
457
	PM_PUSH(EVT10)
458
	PM_PUSH(EVT11)
459
	PM_PUSH(EVT12)
460
	PM_PUSH(EVT13)
461
	PM_PUSH(EVT14)
462
	PM_PUSH(EVT15)
463
	PM_PUSH(IMASK)
464
	PM_PUSH(ILAT)
465
	PM_PUSH(IPRIO)
466
	PM_PUSH(TCNTL)
467
	PM_PUSH(TPERIOD)
468
	PM_PUSH(TSCALE)
469
	PM_PUSH(TCOUNT)
470
	PM_PUSH(TBUFCTL)
471

472
	/* Save Core Registers */
473
	[--sp] = SYSCFG;
474
	[--sp] = ( R7:0, P5:0 );
475
	[--sp] = fp;
476
	[--sp] = usp;
477

478
	[--sp] = i0;
479
	[--sp] = i1;
480
	[--sp] = i2;
481
	[--sp] = i3;
482

483
	[--sp] = m0;
484
	[--sp] = m1;
485
	[--sp] = m2;
486
	[--sp] = m3;
487

488
	[--sp] = l0;
489
	[--sp] = l1;
490
	[--sp] = l2;
491
	[--sp] = l3;
492

493
	[--sp] = b0;
494
	[--sp] = b1;
495
	[--sp] = b2;
496
	[--sp] = b3;
497
	[--sp] = a0.x;
498
	[--sp] = a0.w;
499
	[--sp] = a1.x;
500
	[--sp] = a1.w;
501

502
	[--sp] = LC0;
503
	[--sp] = LC1;
504
	[--sp] = LT0;
505
	[--sp] = LT1;
506
	[--sp] = LB0;
507
	[--sp] = LB1;
508

509
	[--sp] = ASTAT;
510
	[--sp] = CYCLES;
511
	[--sp] = CYCLES2;
512

513
	[--sp] = RETS;
514
	r0 = RETI;
515
	[--sp] = r0;
516
	[--sp] = RETX;
517
	[--sp] = RETN;
518
	[--sp] = RETE;
519
	[--sp] = SEQSTAT;
520

521
	/* Save Magic, return address and Stack Pointer */
522
	P0.H = 0;
523
	P0.L = 0;
524
	R0.H = 0xDEAD;	/* Hibernate Magic */
525
	R0.L = 0xBEEF;
526
	[P0++] = R0;	/* Store Hibernate Magic */
527
	R0.H = .Lpm_resume_here;
528
	R0.L = .Lpm_resume_here;
529
	[P0++] = R0;	/* Save Return Address */
530
	[P0++] = SP;	/* Save Stack Pointer */
531
	P0.H = _hibernate_mode;
532
	P0.L = _hibernate_mode;
533
	R0 = R2;
534
	call (P0); /* Goodbye */
535

536
.Lpm_resume_here:
537

538
	/* Restore Core Registers */
539
	SEQSTAT = [sp++];
540
	RETE = [sp++];
541
	RETN = [sp++];
542
	RETX = [sp++];
543
	r0 = [sp++];
544
	RETI = r0;
545
	RETS = [sp++];
546

547
	CYCLES2 = [sp++];
548
	CYCLES = [sp++];
549
	ASTAT = [sp++];
550

551
	LB1 = [sp++];
552
	LB0 = [sp++];
553
	LT1 = [sp++];
554
	LT0 = [sp++];
555
	LC1 = [sp++];
556
	LC0 = [sp++];
557

558
	a1.w = [sp++];
559
	a1.x = [sp++];
560
	a0.w = [sp++];
561
	a0.x = [sp++];
562
	b3 = [sp++];
563
	b2 = [sp++];
564
	b1 = [sp++];
565
	b0 = [sp++];
566

567
	l3 = [sp++];
568
	l2 = [sp++];
569
	l1 = [sp++];
570
	l0 = [sp++];
571

572
	m3 = [sp++];
573
	m2 = [sp++];
574
	m1 = [sp++];
575
	m0 = [sp++];
576

577
	i3 = [sp++];
578
	i2 = [sp++];
579
	i1 = [sp++];
580
	i0 = [sp++];
581

582
	usp = [sp++];
583
	fp = [sp++];
584

585
	( R7 : 0, P5 : 0) = [ SP ++ ];
586
	SYSCFG = [sp++];
587

588
	/* Restore Core MMRs */
589

590
	PM_POP(TBUFCTL)
591
	PM_POP(TCOUNT)
592
	PM_POP(TSCALE)
593
	PM_POP(TPERIOD)
594
	PM_POP(TCNTL)
595
	PM_POP(IPRIO)
596
	PM_POP(ILAT)
597
	PM_POP(IMASK)
598
	PM_POP(EVT15)
599
	PM_POP(EVT14)
600
	PM_POP(EVT13)
601
	PM_POP(EVT12)
602
	PM_POP(EVT11)
603
	PM_POP(EVT10)
604
	PM_POP(EVT9)
605
	PM_POP(EVT8)
606
	PM_POP(EVT7)
607
	PM_POP(EVT6)
608
	PM_POP(EVT5)
609
	PM_POP(EVT4)
610
	PM_POP(EVT3)
611
	PM_POP(EVT2)
612
	PM_POP(EVT1)
613
	PM_POP(EVT0)
614
	PM_POP(ICPLB_DATA15)
615
	PM_POP(ICPLB_DATA14)
616
	PM_POP(ICPLB_DATA13)
617
	PM_POP(ICPLB_DATA12)
618
	PM_POP(ICPLB_DATA11)
619
	PM_POP(ICPLB_DATA10)
620
	PM_POP(ICPLB_DATA9)
621
	PM_POP(ICPLB_DATA8)
622
	PM_POP(ICPLB_DATA7)
623
	PM_POP(ICPLB_DATA6)
624
	PM_POP(ICPLB_DATA5)
625
	PM_POP(ICPLB_DATA4)
626
	PM_POP(ICPLB_DATA3)
627
	PM_POP(ICPLB_DATA2)
628
	PM_POP(ICPLB_DATA1)
629
	PM_POP(ICPLB_DATA0)
630
	PM_POP(ICPLB_ADDR15)
631
	PM_POP(ICPLB_ADDR14)
632
	PM_POP(ICPLB_ADDR13)
633
	PM_POP(ICPLB_ADDR12)
634
	PM_POP(ICPLB_ADDR11)
635
	PM_POP(ICPLB_ADDR10)
636
	PM_POP(ICPLB_ADDR9)
637
	PM_POP(ICPLB_ADDR8)
638
	PM_POP(ICPLB_ADDR7)
639
	PM_POP(ICPLB_ADDR6)
640
	PM_POP(ICPLB_ADDR5)
641
	PM_POP(ICPLB_ADDR4)
642
	PM_POP(ICPLB_ADDR3)
643
	PM_POP(ICPLB_ADDR2)
644
	PM_POP(ICPLB_ADDR1)
645
	PM_POP(ICPLB_ADDR0)
646
	PM_POP(IMEM_CONTROL)
647
	PM_POP(DCPLB_DATA15)
648
	PM_POP(DCPLB_DATA14)
649
	PM_POP(DCPLB_DATA13)
650
	PM_POP(DCPLB_DATA12)
651
	PM_POP(DCPLB_DATA11)
652
	PM_POP(DCPLB_DATA10)
653
	PM_POP(DCPLB_DATA9)
654
	PM_POP(DCPLB_DATA8)
655
	PM_POP(DCPLB_DATA7)
656
	PM_POP(DCPLB_DATA6)
657
	PM_POP(DCPLB_DATA5)
658
	PM_POP(DCPLB_DATA4)
659
	PM_POP(DCPLB_DATA3)
660
	PM_POP(DCPLB_DATA2)
661
	PM_POP(DCPLB_DATA1)
662
	PM_POP(DCPLB_DATA0)
663
	PM_POP(DCPLB_ADDR15)
664
	PM_POP(DCPLB_ADDR14)
665
	PM_POP(DCPLB_ADDR13)
666
	PM_POP(DCPLB_ADDR12)
667
	PM_POP(DCPLB_ADDR11)
668
	PM_POP(DCPLB_ADDR10)
669
	PM_POP(DCPLB_ADDR9)
670
	PM_POP(DCPLB_ADDR8)
671
	PM_POP(DCPLB_ADDR7)
672
	PM_POP(DCPLB_ADDR6)
673
	PM_POP(DCPLB_ADDR5)
674
	PM_POP(DCPLB_ADDR4)
675
	PM_POP(DCPLB_ADDR3)
676
	PM_POP(DCPLB_ADDR2)
677
	PM_POP(DCPLB_ADDR1)
678
	PM_POP(DCPLB_ADDR0)
679
	PM_POP(DMEM_CONTROL)
680

681
	/* Restore System MMRs */
682

683
	P0.H = hi(PLL_CTL);
684
	P0.L = lo(PLL_CTL);
685
	PM_SYS_POP16(SYSCR)
686

687
#ifdef PORTCIO_FER
688
	PM_SYS_POP16(PORTEIO_FER)
689
	PM_SYS_POP16(PORTEIO)
690
	PM_SYS_POP16(PORTEIO_INEN)
691
	PM_SYS_POP16(PORTEIO_DIR)
692
	PM_SYS_POP16(PORTDIO_FER)
693
	PM_SYS_POP16(PORTDIO)
694
	PM_SYS_POP16(PORTDIO_INEN)
695
	PM_SYS_POP16(PORTDIO_DIR)
696
	PM_SYS_POP16(PORTCIO_FER)
697
	PM_SYS_POP16(PORTCIO)
698
	PM_SYS_POP16(PORTCIO_INEN)
699
	PM_SYS_POP16(PORTCIO_DIR)
700
#endif
701

702
#ifdef EBIU_FCTL
703
	PM_SYS_POP(EBIU_FCTL)
704
	PM_SYS_POP(EBIU_MODE)
705
	PM_SYS_POP(EBIU_MBSCTL)
706
#endif
707
	PM_SYS_POP16(EBIU_AMGCTL)
708
	PM_SYS_POP(EBIU_AMBCTL1)
709
	PM_SYS_POP(EBIU_AMBCTL0)
710

711
#ifdef PINT0_ASSIGN
712
	PM_SYS_POP(PINT3_EDGE_SET)
713
	PM_SYS_POP(PINT2_EDGE_SET)
714
	PM_SYS_POP(PINT1_EDGE_SET)
715
	PM_SYS_POP(PINT0_EDGE_SET)
716
	PM_SYS_POP(PINT3_INVERT_SET)
717
	PM_SYS_POP(PINT2_INVERT_SET)
718
	PM_SYS_POP(PINT1_INVERT_SET)
719
	PM_SYS_POP(PINT0_INVERT_SET)
720
	PM_SYS_POP(PINT3_ASSIGN)
721
	PM_SYS_POP(PINT2_ASSIGN)
722
	PM_SYS_POP(PINT1_ASSIGN)
723
	PM_SYS_POP(PINT0_ASSIGN)
724
	PM_SYS_POP(PINT3_MASK_SET)
725
	PM_SYS_POP(PINT2_MASK_SET)
726
	PM_SYS_POP(PINT1_MASK_SET)
727
	PM_SYS_POP(PINT0_MASK_SET)
728
#endif
729

730
#ifdef SIC_IWR2
731
	PM_SYS_POP(SIC_IWR2)
732
#endif
733
#ifdef SIC_IWR1
734
	PM_SYS_POP(SIC_IWR1)
735
#endif
736
#ifdef SIC_IWR0
737
	PM_SYS_POP(SIC_IWR0)
738
#endif
739
#ifdef SIC_IWR
740
	PM_SYS_POP(SIC_IWR)
741
#endif
742

743
#ifdef SIC_IAR8
744
	PM_SYS_POP(SIC_IAR11)
745
	PM_SYS_POP(SIC_IAR10)
746
	PM_SYS_POP(SIC_IAR9)
747
	PM_SYS_POP(SIC_IAR8)
748
#endif
749
#ifdef SIC_IAR7
750
	PM_SYS_POP(SIC_IAR7)
751
#endif
752
#ifdef SIC_IAR6
753
	PM_SYS_POP(SIC_IAR6)
754
	PM_SYS_POP(SIC_IAR5)
755
	PM_SYS_POP(SIC_IAR4)
756
#endif
757
#ifdef SIC_IAR3
758
	PM_SYS_POP(SIC_IAR3)
759
#endif
760
#ifdef SIC_IAR0
761
	PM_SYS_POP(SIC_IAR2)
762
	PM_SYS_POP(SIC_IAR1)
763
	PM_SYS_POP(SIC_IAR0)
764
#endif
765
#ifdef SIC_IMASK
766
	PM_SYS_POP(SIC_IMASK)
767
#endif
768
#ifdef SIC_IMASK2
769
	PM_SYS_POP(SIC_IMASK2)
770
#endif
771
#ifdef SIC_IMASK1
772
	PM_SYS_POP(SIC_IMASK1)
773
#endif
774
#ifdef SIC_IMASK0
775
	PM_SYS_POP(SIC_IMASK0)
776
#endif
777

778
	[--sp] = RETI;	/* Clear Global Interrupt Disable */
779
	SP += 4;
780

781
	RETS = [SP++];
782
	( R7:0, P5:0 ) = [SP++];
783
	RTS;
784
ENDPROC(_do_hibernate)
785

786
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