Path: blob/master/arch/cris/arch-v10/lib/dram_init.S
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/*1* DRAM/SDRAM initialization - alter with care2* This file is intended to be included from other assembler files3*4* Note: This file may not modify r9 because r9 is used to carry5* information from the decompresser to the kernel6*7* Copyright (C) 2000, 2001 Axis Communications AB8*9* Authors: Mikael Starvik ([email protected])10*11*/1213/* Just to be certain the config file is included, we include it here14* explicitly instead of depending on it being included in the file that15* uses this code.16*/171819;; WARNING! The registers r8 and r9 are used as parameters carrying20;; information from the decompressor (if the kernel was compressed).21;; They should not be used in the code below.2223#ifndef CONFIG_SVINTO_SIM24move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r025move.d $r0, [R_WAITSTATES]2627move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r028move.d $r0, [R_BUS_CONFIG]2930#ifndef CONFIG_ETRAX_SDRAM31move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r032move.d $r0, [R_DRAM_CONFIG]3334move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r035move.d $r0, [R_DRAM_TIMING]36#else37;; Samsung SDRAMs seem to require to be initialized twice to work properly.38moveq 2, $r639_sdram_init:4041; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization4243; Bank configuration44move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r045move.d $r0, [R_SDRAM_CONFIG]4647; Calculate value of mrs_data48; CAS latency = 2 && bus_width = 32 => 0x4049; CAS latency = 3 && bus_width = 32 => 0x6050; CAS latency = 2 && bus_width = 16 => 0x2051; CAS latency = 3 && bus_width = 16 => 0x305253; Check if value is already supplied in kernel config54move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r255and.d 0x00ff0000, $r256bne _set_timing57lsrq 16, $r25859move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 260move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r161move.d $r1, $r362and.d 0x03, $r1 ; Get CAS latency63and.d 0x1000, $r3 ; 50 or 100 MHz?64beq _speed_5065nop66_speed_100:67cmp.d 0x00, $r1 ; CAS latency = 2?68beq _bw_check69nop70or.d 0x20, $r2 ; CAS latency = 371ba _bw_check72nop73_speed_50:74cmp.d 0x01, $r1 ; CAS latency = 2?75beq _bw_check76nop77or.d 0x20, $r2 ; CAS latency = 378_bw_check:79move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r180and.d 0x800000, $r1 ; DRAM width is bit 2381bne _set_timing82nop83lsrq 1, $r2 ; 16 bits. Shift down value.8485; Set timing parameters. Starts master clock86_set_timing:87move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r188and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 089or.d 0x80000000, $r1 ; Make sure sdram enable bit is set90move.d $r1, $r591or.d 0x0000c000, $r1 ; ref = disable92lslq 16, $r2 ; mrs data starts at bit 1693or.d $r2, $r194move.d $r1, [R_SDRAM_TIMING]9596; Wait 200us97move.d 10000, $r2981: bne 1b99subq 1, $r2100101; Issue initialization command sequence102move.d _sdram_commands_start, $r2103and.d 0x000fffff, $r2 ; Make sure commands are read from flash104move.d _sdram_commands_end, $r3105and.d 0x000fffff, $r31061: clear.d $r4107move.b [$r2+], $r4108lslq 9, $r4 ; Command starts at bit 9109or.d $r1, $r4110move.d $r4, [R_SDRAM_TIMING]111nop ; Wait five nop cycles between each command112nop113nop114nop115nop116cmp.d $r2, $r3117bne 1b118nop119move.d $r5, [R_SDRAM_TIMING]120subq 1, $r6121bne _sdram_init122nop123ba _sdram_commands_end124nop125126_sdram_commands_start:127.byte 3 ; Precharge128.byte 0 ; nop129.byte 2 ; refresh130.byte 0 ; nop131.byte 2 ; refresh132.byte 0 ; nop133.byte 2 ; refresh134.byte 0 ; nop135.byte 2 ; refresh136.byte 0 ; nop137.byte 2 ; refresh138.byte 0 ; nop139.byte 2 ; refresh140.byte 0 ; nop141.byte 2 ; refresh142.byte 0 ; nop143.byte 2 ; refresh144.byte 0 ; nop145.byte 1 ; mrs146.byte 0 ; nop147_sdram_commands_end:148#endif149#endif150151152