CoCalc -- nand

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/cris/arch-v32/lib/nand_init.S
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##=============================================================================
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##
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##      nand_init.S
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##
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##      The bootrom copies data from the NAND flash to the internal RAM but
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##      due to a bug/feature we can only trust the 256 first bytes. So this
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##      code copies more data from NAND flash to internal RAM. Obvioulsy this
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##      code must fit in the first 256 bytes so alter with care.
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##
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##	Some notes about the bug/feature for future reference:
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##        The bootrom copies the first 127 KB from NAND flash to internal
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##        memory. The problem is that it does a bytewise copy. NAND flashes
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##        does autoincrement on the address so for a 16-bite device each
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##        read/write increases the address by two. So the copy loop in the
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##        bootrom will discard every second byte. This is solved by inserting
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##        zeroes in every second byte in the first erase block.
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##
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##        The bootrom also incorrectly assumes that it can read the flash
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##        linear with only one read command but the flash will actually
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##        switch between normal area and spare area if you do that so we
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##        can't trust more than the first 256 bytes.
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##
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##=============================================================================
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#include <arch/hwregs/asm/reg_map_asm.h>
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#include <arch/hwregs/asm/gio_defs_asm.h>
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#include <arch/hwregs/asm/pinmux_defs_asm.h>
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#include <arch/hwregs/asm/bif_core_defs_asm.h>
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#include <arch/hwregs/asm/config_defs_asm.h>
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;; There are 8-bit NAND flashes and 16-bit NAND flashes.
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;; We need to treat them slightly different.
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#if CONFIG_ETRAX_FLASH_BUSWIDTH==2
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#define PAGE_SIZE 256
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#else
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#error 2
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#define PAGE_SIZE 512
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#endif
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#define ERASE_BLOCK 16384
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;; GPIO pins connected to NAND flash
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#define CE 4
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#define CLE 5
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#define ALE 6
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#define BY 7
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;; Address space for NAND flash
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#define NAND_RD_ADDR 0x90000000
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#define NAND_WR_ADDR 0x94000000
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#define READ_CMD 0x00
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;; Readability macros
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#define CSP_MASK \
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	REG_MASK(bif_core, rw_grp3_cfg, gated_csp0) | \
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	REG_MASK(bif_core, rw_grp3_cfg, gated_csp1)
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#define CSP_VAL \
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	REG_STATE(bif_core, rw_grp3_cfg, gated_csp0, rd) | \
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	REG_STATE(bif_core, rw_grp3_cfg, gated_csp1, wr)
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;;----------------------------------------------------------------------------
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;; Macros to set/clear GPIO bits
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.macro SET x
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	or.b   (1<<\x),$r9
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	move.d $r9, [$r2]
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.endm
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.macro CLR x
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	and.b  ~(1<<\x),$r9
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	move.d $r9, [$r2]
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.endm
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;;----------------------------------------------------------------------------
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nand_boot:
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	;; Check if nand boot was selected
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	move.d REG_ADDR(config, regi_config, r_bootsel), $r0
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	move.d [$r0], $r0
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	and.d  REG_MASK(config, r_bootsel, boot_mode), $r0
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	cmp.d  REG_STATE(config, r_bootsel, boot_mode, nand), $r0
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	bne normal_boot ; No NAND boot
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	nop
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copy_nand_to_ram:
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	;; copy_nand_to_ram
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	;; Arguments
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	;;   r10 - destination
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	;;   r11 - source offset
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	;;   r12 - size
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	;;   r13 - Address to jump to after completion
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	;; Note : r10-r12 are clobbered on return
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	;; Registers used:
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	;;   r0 - NAND_RD_ADDR
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	;;   r1 - NAND_WR_ADDR
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	;;   r2 - reg_gio_rw_pa_dout
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	;;   r3 - reg_gio_r_pa_din
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	;;   r4 - tmp
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	;;   r5 - byte counter within a page
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	;;   r6 - reg_pinmux_rw_pa
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	;;   r7 - reg_gio_rw_pa_oe
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	;;   r8 - reg_bif_core_rw_grp3_cfg
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	;;   r9 - reg_gio_rw_pa_dout shadow
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	move.d 0x90000000, $r0
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	move.d 0x94000000, $r1
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	move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r2
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	move.d REG_ADDR(gio, regi_gio, r_pa_din), $r3
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	move.d REG_ADDR(pinmux, regi_pinmux, rw_pa), $r6
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	move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r7
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	move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r8
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#if CONFIG_ETRAX_FLASH_BUSWIDTH==2
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	lsrq	1, $r11
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#endif
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	;; Set up GPIO
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	move.d [$r2], $r9
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	move.d [$r7], $r4
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	or.b (1<<ALE) | (1 << CLE) | (1<<CE), $r4
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	move.d $r4, [$r7]
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	;; Set up bif
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	move.d [$r8], $r4
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	and.d CSP_MASK, $r4
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	or.d CSP_VAL, $r4
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	move.d $r4, [$r8]
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1:	;; Copy one page
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	CLR CE
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	SET CLE
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	moveq	READ_CMD, $r4
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	move.b	$r4, [$r1]
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	moveq	20, $r4
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2:	bne	2b
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	subq	1, $r4
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	CLR CLE
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	SET ALE
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	clear.w [$r1] 		; Column address = 0
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	move.d	$r11, $r4
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	lsrq	8, $r4
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	move.b	$r4, [$r1]	; Row address
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	lsrq	8, $r4
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	move.b	$r4, [$r1]	; Row address
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	moveq	20, $r4
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2:	bne	2b
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	subq	1, $r4
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	CLR ALE
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2:	move.d	[$r3], $r4
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	and.d	1 << BY, $r4
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	beq 2b
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	movu.w  PAGE_SIZE, $r5
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2:	; Copy one byte/word
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#if CONFIG_ETRAX_FLASH_BUSWIDTH==2
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	move.w  [$r0], $r4
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#else
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	move.b  [$r0], $r4
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#endif
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	subq	1, $r5
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	bne	2b
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#if CONFIG_ETRAX_FLASH_BUSWIDTH==2
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	move.w  $r4, [$r10+]
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	subu.w	PAGE_SIZE*2, $r12
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#else
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	move.b  $r4, [$r10+]
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	subu.w	PAGE_SIZE, $r12
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#endif
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	bpl	1b
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	addu.w	PAGE_SIZE, $r11
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	;; End of copy
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	jump	$r13
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	nop
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	;; This will warn if the code above is too large. If you consider
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	;; to remove this you don't understand the bug/feature.
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	.org 256
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	.org ERASE_BLOCK
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normal_boot:
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