CoCalc -- dram

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/cris/arch-v32/mach-fs/dram_init.S
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/*
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 * DRAM/SDRAM initialization - alter with care
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 * This file is intended to be included from other assembler files
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 *
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 * Note: This file may not modify r8 or r9 because they are used to
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 * carry information from the decompresser to the kernel
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 *
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 * Copyright (C) 2000-2007 Axis Communications AB
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 *
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 * Authors:  Mikael Starvik <[email protected]>
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 */
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/* Just to be certain the config file is included, we include it here
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 * explicitely instead of depending on it being included in the file that
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 * uses this code.
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 */
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#include <hwregs/asm/reg_map_asm.h>
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#include <hwregs/asm/bif_core_defs_asm.h>
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	;; WARNING! The registers r8 and r9 are used as parameters carrying
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	;; information from the decompressor (if the kernel was compressed).
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	;; They should not be used in the code below.
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	; Refer to BIF MDS for a description of SDRAM initialization
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	; Bank configuration
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	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
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	move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
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	move.d   $r1, [$r0]
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	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
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	move.d   CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
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	move.d   $r1, [$r0]
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	; Calculate value of mrs_data
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	; CAS latency = 2 && bus_width = 32 => 0x40
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	; CAS latency = 3 && bus_width = 32 => 0x60
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	; CAS latency = 2 && bus_width = 16 => 0x20
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	; CAS latency = 3 && bus_width = 16 => 0x30
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	; Check if value is already supplied in kernel config
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	move.d   CONFIG_ETRAX_SDRAM_COMMAND, $r2
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	bne	 _set_timing
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	nop
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	move.d   0x40, $r4       ; Assume 32 bits and CAS latency = 2
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	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
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	and.d    0x07, $r1       ; Get CAS latency
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	cmpq	 2, $r1		 ; CL = 2 ?
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	beq	 _bw_check
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	nop
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	move.d   0x60, $r4
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_bw_check:
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	; Assume that group 0 width is equal to group 1. This assumption
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	; is wrong for a group 1 only hardware (such as the grand old
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	; StorPoint+).
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	move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
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	and.d    0x200, $r1	; DRAM width is bit 9
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	beq      _set_timing
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	lslq	 2, $r4		;  mrs_data starts at bit 2
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	lsrq     1, $r4		;  16 bits. Shift down value.
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	; Set timing parameters (refresh off to avoid Guinness TR 83)
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_set_timing:
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	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
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	and.d    ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
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	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
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	move.d   $r1, [$r0]
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	; Issue NOP command
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	move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
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	moveq regk_bif_core_nop, $r1
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	move.d $r1, [$r5]
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	; Wait 200us
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	move.d   10000, $r2
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1:	bne      1b
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	subq     1, $r2
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	; Issue initialization command sequence
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	lapc     _sdram_commands_start, $r2
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	lapc     _sdram_commands_end,  $r3
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1:	clear.d  $r6
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	move.b   [$r2+], $r6	; Load command
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	or.d     $r4, $r6	; Add calculated mrs
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	move.d   $r6, [$r5]	; Write rw_sdram_cmd
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	; Wait 80 ns between each command
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	move.d	 4000, $r7
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2:	bne	 2b
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	subq	 1, $r7
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	cmp.d    $r2, $r3	; Last command?
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	bne      1b
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	nop
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	; Start refresh
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	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
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	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
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	move.d   $r1, [$r0]
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	; Initialization finished
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	ba       _sdram_commands_end
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	nop
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_sdram_commands_start:
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	.byte   regk_bif_core_pre ; Precharge
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	.byte   regk_bif_core_ref ; refresh
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	.byte   regk_bif_core_ref ; refresh
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	.byte   regk_bif_core_ref ; refresh
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	.byte   regk_bif_core_ref ; refresh
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	.byte   regk_bif_core_ref ; refresh
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	.byte   regk_bif_core_ref ; refresh
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	.byte   regk_bif_core_ref ; refresh
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	.byte   regk_bif_core_ref ; refresh
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	.byte   regk_bif_core_mrs ; mrs
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_sdram_commands_end:
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