Path: blob/master/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h
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#ifndef __gio_defs_h1#define __gio_defs_h23/*4* This file is autogenerated from5* file: gio.r6*7* by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r8* Any changes here will be lost.9*10* -*- buffer-read-only: t -*-11*/12/* Main access macros */13#ifndef REG_RD14#define REG_RD( scope, inst, reg ) \15REG_READ( reg_##scope##_##reg, \16(inst) + REG_RD_ADDR_##scope##_##reg )17#endif1819#ifndef REG_WR20#define REG_WR( scope, inst, reg, val ) \21REG_WRITE( reg_##scope##_##reg, \22(inst) + REG_WR_ADDR_##scope##_##reg, (val) )23#endif2425#ifndef REG_RD_VECT26#define REG_RD_VECT( scope, inst, reg, index ) \27REG_READ( reg_##scope##_##reg, \28(inst) + REG_RD_ADDR_##scope##_##reg + \29(index) * STRIDE_##scope##_##reg )30#endif3132#ifndef REG_WR_VECT33#define REG_WR_VECT( scope, inst, reg, index, val ) \34REG_WRITE( reg_##scope##_##reg, \35(inst) + REG_WR_ADDR_##scope##_##reg + \36(index) * STRIDE_##scope##_##reg, (val) )37#endif3839#ifndef REG_RD_INT40#define REG_RD_INT( scope, inst, reg ) \41REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )42#endif4344#ifndef REG_WR_INT45#define REG_WR_INT( scope, inst, reg, val ) \46REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )47#endif4849#ifndef REG_RD_INT_VECT50#define REG_RD_INT_VECT( scope, inst, reg, index ) \51REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \52(index) * STRIDE_##scope##_##reg )53#endif5455#ifndef REG_WR_INT_VECT56#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \57REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \58(index) * STRIDE_##scope##_##reg, (val) )59#endif6061#ifndef REG_TYPE_CONV62#define REG_TYPE_CONV( type, orgtype, val ) \63( { union { orgtype o; type n; } r; r.o = val; r.n; } )64#endif6566#ifndef reg_page_size67#define reg_page_size 819268#endif6970#ifndef REG_ADDR71#define REG_ADDR( scope, inst, reg ) \72( (inst) + REG_RD_ADDR_##scope##_##reg )73#endif7475#ifndef REG_ADDR_VECT76#define REG_ADDR_VECT( scope, inst, reg, index ) \77( (inst) + REG_RD_ADDR_##scope##_##reg + \78(index) * STRIDE_##scope##_##reg )79#endif8081/* C-code for register scope gio */8283/* Register r_pa_din, scope gio, type r */84typedef struct {85unsigned int data : 32;86} reg_gio_r_pa_din;87#define REG_RD_ADDR_gio_r_pa_din 08889/* Register rw_pa_dout, scope gio, type rw */90typedef struct {91unsigned int data : 32;92} reg_gio_rw_pa_dout;93#define REG_RD_ADDR_gio_rw_pa_dout 494#define REG_WR_ADDR_gio_rw_pa_dout 49596/* Register rw_pa_oe, scope gio, type rw */97typedef struct {98unsigned int oe : 32;99} reg_gio_rw_pa_oe;100#define REG_RD_ADDR_gio_rw_pa_oe 8101#define REG_WR_ADDR_gio_rw_pa_oe 8102103/* Register rw_pa_byte0_dout, scope gio, type rw */104typedef struct {105unsigned int data : 8;106unsigned int dummy1 : 24;107} reg_gio_rw_pa_byte0_dout;108#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12109#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12110111/* Register rw_pa_byte0_oe, scope gio, type rw */112typedef struct {113unsigned int oe : 8;114unsigned int dummy1 : 24;115} reg_gio_rw_pa_byte0_oe;116#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16117#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16118119/* Register rw_pa_byte1_dout, scope gio, type rw */120typedef struct {121unsigned int data : 8;122unsigned int dummy1 : 24;123} reg_gio_rw_pa_byte1_dout;124#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20125#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20126127/* Register rw_pa_byte1_oe, scope gio, type rw */128typedef struct {129unsigned int oe : 8;130unsigned int dummy1 : 24;131} reg_gio_rw_pa_byte1_oe;132#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24133#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24134135/* Register rw_pa_byte2_dout, scope gio, type rw */136typedef struct {137unsigned int data : 8;138unsigned int dummy1 : 24;139} reg_gio_rw_pa_byte2_dout;140#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28141#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28142143/* Register rw_pa_byte2_oe, scope gio, type rw */144typedef struct {145unsigned int oe : 8;146unsigned int dummy1 : 24;147} reg_gio_rw_pa_byte2_oe;148#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32149#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32150151/* Register rw_pa_byte3_dout, scope gio, type rw */152typedef struct {153unsigned int data : 8;154unsigned int dummy1 : 24;155} reg_gio_rw_pa_byte3_dout;156#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36157#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36158159/* Register rw_pa_byte3_oe, scope gio, type rw */160typedef struct {161unsigned int oe : 8;162unsigned int dummy1 : 24;163} reg_gio_rw_pa_byte3_oe;164#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40165#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40166167/* Register r_pb_din, scope gio, type r */168typedef struct {169unsigned int data : 32;170} reg_gio_r_pb_din;171#define REG_RD_ADDR_gio_r_pb_din 44172173/* Register rw_pb_dout, scope gio, type rw */174typedef struct {175unsigned int data : 32;176} reg_gio_rw_pb_dout;177#define REG_RD_ADDR_gio_rw_pb_dout 48178#define REG_WR_ADDR_gio_rw_pb_dout 48179180/* Register rw_pb_oe, scope gio, type rw */181typedef struct {182unsigned int oe : 32;183} reg_gio_rw_pb_oe;184#define REG_RD_ADDR_gio_rw_pb_oe 52185#define REG_WR_ADDR_gio_rw_pb_oe 52186187/* Register rw_pb_byte0_dout, scope gio, type rw */188typedef struct {189unsigned int data : 8;190unsigned int dummy1 : 24;191} reg_gio_rw_pb_byte0_dout;192#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56193#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56194195/* Register rw_pb_byte0_oe, scope gio, type rw */196typedef struct {197unsigned int oe : 8;198unsigned int dummy1 : 24;199} reg_gio_rw_pb_byte0_oe;200#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60201#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60202203/* Register rw_pb_byte1_dout, scope gio, type rw */204typedef struct {205unsigned int data : 8;206unsigned int dummy1 : 24;207} reg_gio_rw_pb_byte1_dout;208#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64209#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64210211/* Register rw_pb_byte1_oe, scope gio, type rw */212typedef struct {213unsigned int oe : 8;214unsigned int dummy1 : 24;215} reg_gio_rw_pb_byte1_oe;216#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68217#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68218219/* Register rw_pb_byte2_dout, scope gio, type rw */220typedef struct {221unsigned int data : 8;222unsigned int dummy1 : 24;223} reg_gio_rw_pb_byte2_dout;224#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72225#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72226227/* Register rw_pb_byte2_oe, scope gio, type rw */228typedef struct {229unsigned int oe : 8;230unsigned int dummy1 : 24;231} reg_gio_rw_pb_byte2_oe;232#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76233#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76234235/* Register rw_pb_byte3_dout, scope gio, type rw */236typedef struct {237unsigned int data : 8;238unsigned int dummy1 : 24;239} reg_gio_rw_pb_byte3_dout;240#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80241#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80242243/* Register rw_pb_byte3_oe, scope gio, type rw */244typedef struct {245unsigned int oe : 8;246unsigned int dummy1 : 24;247} reg_gio_rw_pb_byte3_oe;248#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84249#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84250251/* Register r_pc_din, scope gio, type r */252typedef struct {253unsigned int data : 16;254unsigned int dummy1 : 16;255} reg_gio_r_pc_din;256#define REG_RD_ADDR_gio_r_pc_din 88257258/* Register rw_pc_dout, scope gio, type rw */259typedef struct {260unsigned int data : 16;261unsigned int dummy1 : 16;262} reg_gio_rw_pc_dout;263#define REG_RD_ADDR_gio_rw_pc_dout 92264#define REG_WR_ADDR_gio_rw_pc_dout 92265266/* Register rw_pc_oe, scope gio, type rw */267typedef struct {268unsigned int oe : 16;269unsigned int dummy1 : 16;270} reg_gio_rw_pc_oe;271#define REG_RD_ADDR_gio_rw_pc_oe 96272#define REG_WR_ADDR_gio_rw_pc_oe 96273274/* Register rw_pc_byte0_dout, scope gio, type rw */275typedef struct {276unsigned int data : 8;277unsigned int dummy1 : 24;278} reg_gio_rw_pc_byte0_dout;279#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100280#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100281282/* Register rw_pc_byte0_oe, scope gio, type rw */283typedef struct {284unsigned int oe : 8;285unsigned int dummy1 : 24;286} reg_gio_rw_pc_byte0_oe;287#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104288#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104289290/* Register rw_pc_byte1_dout, scope gio, type rw */291typedef struct {292unsigned int data : 8;293unsigned int dummy1 : 24;294} reg_gio_rw_pc_byte1_dout;295#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108296#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108297298/* Register rw_pc_byte1_oe, scope gio, type rw */299typedef struct {300unsigned int oe : 8;301unsigned int dummy1 : 24;302} reg_gio_rw_pc_byte1_oe;303#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112304#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112305306/* Register r_pd_din, scope gio, type r */307typedef struct {308unsigned int data : 32;309} reg_gio_r_pd_din;310#define REG_RD_ADDR_gio_r_pd_din 116311312/* Register rw_intr_cfg, scope gio, type rw */313typedef struct {314unsigned int intr0 : 3;315unsigned int intr1 : 3;316unsigned int intr2 : 3;317unsigned int intr3 : 3;318unsigned int intr4 : 3;319unsigned int intr5 : 3;320unsigned int intr6 : 3;321unsigned int intr7 : 3;322unsigned int dummy1 : 8;323} reg_gio_rw_intr_cfg;324#define REG_RD_ADDR_gio_rw_intr_cfg 120325#define REG_WR_ADDR_gio_rw_intr_cfg 120326327/* Register rw_intr_pins, scope gio, type rw */328typedef struct {329unsigned int intr0 : 4;330unsigned int intr1 : 4;331unsigned int intr2 : 4;332unsigned int intr3 : 4;333unsigned int intr4 : 4;334unsigned int intr5 : 4;335unsigned int intr6 : 4;336unsigned int intr7 : 4;337} reg_gio_rw_intr_pins;338#define REG_RD_ADDR_gio_rw_intr_pins 124339#define REG_WR_ADDR_gio_rw_intr_pins 124340341/* Register rw_intr_mask, scope gio, type rw */342typedef struct {343unsigned int intr0 : 1;344unsigned int intr1 : 1;345unsigned int intr2 : 1;346unsigned int intr3 : 1;347unsigned int intr4 : 1;348unsigned int intr5 : 1;349unsigned int intr6 : 1;350unsigned int intr7 : 1;351unsigned int i2c0_done : 1;352unsigned int i2c1_done : 1;353unsigned int dummy1 : 22;354} reg_gio_rw_intr_mask;355#define REG_RD_ADDR_gio_rw_intr_mask 128356#define REG_WR_ADDR_gio_rw_intr_mask 128357358/* Register rw_ack_intr, scope gio, type rw */359typedef struct {360unsigned int intr0 : 1;361unsigned int intr1 : 1;362unsigned int intr2 : 1;363unsigned int intr3 : 1;364unsigned int intr4 : 1;365unsigned int intr5 : 1;366unsigned int intr6 : 1;367unsigned int intr7 : 1;368unsigned int i2c0_done : 1;369unsigned int i2c1_done : 1;370unsigned int dummy1 : 22;371} reg_gio_rw_ack_intr;372#define REG_RD_ADDR_gio_rw_ack_intr 132373#define REG_WR_ADDR_gio_rw_ack_intr 132374375/* Register r_intr, scope gio, type r */376typedef struct {377unsigned int intr0 : 1;378unsigned int intr1 : 1;379unsigned int intr2 : 1;380unsigned int intr3 : 1;381unsigned int intr4 : 1;382unsigned int intr5 : 1;383unsigned int intr6 : 1;384unsigned int intr7 : 1;385unsigned int i2c0_done : 1;386unsigned int i2c1_done : 1;387unsigned int dummy1 : 22;388} reg_gio_r_intr;389#define REG_RD_ADDR_gio_r_intr 136390391/* Register r_masked_intr, scope gio, type r */392typedef struct {393unsigned int intr0 : 1;394unsigned int intr1 : 1;395unsigned int intr2 : 1;396unsigned int intr3 : 1;397unsigned int intr4 : 1;398unsigned int intr5 : 1;399unsigned int intr6 : 1;400unsigned int intr7 : 1;401unsigned int i2c0_done : 1;402unsigned int i2c1_done : 1;403unsigned int dummy1 : 22;404} reg_gio_r_masked_intr;405#define REG_RD_ADDR_gio_r_masked_intr 140406407/* Register rw_i2c0_start, scope gio, type rw */408typedef struct {409unsigned int run : 1;410unsigned int dummy1 : 31;411} reg_gio_rw_i2c0_start;412#define REG_RD_ADDR_gio_rw_i2c0_start 144413#define REG_WR_ADDR_gio_rw_i2c0_start 144414415/* Register rw_i2c0_cfg, scope gio, type rw */416typedef struct {417unsigned int en : 1;418unsigned int bit_order : 1;419unsigned int scl_io : 1;420unsigned int scl_inv : 1;421unsigned int sda_io : 1;422unsigned int sda_idle : 1;423unsigned int dummy1 : 26;424} reg_gio_rw_i2c0_cfg;425#define REG_RD_ADDR_gio_rw_i2c0_cfg 148426#define REG_WR_ADDR_gio_rw_i2c0_cfg 148427428/* Register rw_i2c0_ctrl, scope gio, type rw */429typedef struct {430unsigned int trf_bits : 6;431unsigned int switch_dir : 6;432unsigned int extra_start : 3;433unsigned int early_end : 1;434unsigned int start_stop : 1;435unsigned int ack_dir0 : 1;436unsigned int ack_dir1 : 1;437unsigned int ack_dir2 : 1;438unsigned int ack_dir3 : 1;439unsigned int ack_dir4 : 1;440unsigned int ack_dir5 : 1;441unsigned int ack_bit : 1;442unsigned int start_bit : 1;443unsigned int freq : 2;444unsigned int dummy1 : 5;445} reg_gio_rw_i2c0_ctrl;446#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152447#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152448449/* Register rw_i2c0_data, scope gio, type rw */450typedef struct {451unsigned int data0 : 8;452unsigned int data1 : 8;453unsigned int data2 : 8;454unsigned int data3 : 8;455} reg_gio_rw_i2c0_data;456#define REG_RD_ADDR_gio_rw_i2c0_data 156457#define REG_WR_ADDR_gio_rw_i2c0_data 156458459/* Register rw_i2c0_data2, scope gio, type rw */460typedef struct {461unsigned int data4 : 8;462unsigned int data5 : 8;463unsigned int start_val : 6;464unsigned int ack_val : 6;465unsigned int dummy1 : 4;466} reg_gio_rw_i2c0_data2;467#define REG_RD_ADDR_gio_rw_i2c0_data2 160468#define REG_WR_ADDR_gio_rw_i2c0_data2 160469470/* Register rw_i2c1_start, scope gio, type rw */471typedef struct {472unsigned int run : 1;473unsigned int dummy1 : 31;474} reg_gio_rw_i2c1_start;475#define REG_RD_ADDR_gio_rw_i2c1_start 164476#define REG_WR_ADDR_gio_rw_i2c1_start 164477478/* Register rw_i2c1_cfg, scope gio, type rw */479typedef struct {480unsigned int en : 1;481unsigned int bit_order : 1;482unsigned int scl_io : 1;483unsigned int scl_inv : 1;484unsigned int sda0_io : 1;485unsigned int sda0_idle : 1;486unsigned int sda1_io : 1;487unsigned int sda1_idle : 1;488unsigned int sda2_io : 1;489unsigned int sda2_idle : 1;490unsigned int sda3_io : 1;491unsigned int sda3_idle : 1;492unsigned int sda_sel : 2;493unsigned int sen_idle : 1;494unsigned int sen_inv : 1;495unsigned int sen_sel : 2;496unsigned int dummy1 : 14;497} reg_gio_rw_i2c1_cfg;498#define REG_RD_ADDR_gio_rw_i2c1_cfg 168499#define REG_WR_ADDR_gio_rw_i2c1_cfg 168500501/* Register rw_i2c1_ctrl, scope gio, type rw */502typedef struct {503unsigned int trf_bits : 6;504unsigned int switch_dir : 6;505unsigned int extra_start : 3;506unsigned int early_end : 1;507unsigned int start_stop : 1;508unsigned int ack_dir0 : 1;509unsigned int ack_dir1 : 1;510unsigned int ack_dir2 : 1;511unsigned int ack_dir3 : 1;512unsigned int ack_dir4 : 1;513unsigned int ack_dir5 : 1;514unsigned int ack_bit : 1;515unsigned int start_bit : 1;516unsigned int freq : 2;517unsigned int dummy1 : 5;518} reg_gio_rw_i2c1_ctrl;519#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172520#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172521522/* Register rw_i2c1_data, scope gio, type rw */523typedef struct {524unsigned int data0 : 8;525unsigned int data1 : 8;526unsigned int data2 : 8;527unsigned int data3 : 8;528} reg_gio_rw_i2c1_data;529#define REG_RD_ADDR_gio_rw_i2c1_data 176530#define REG_WR_ADDR_gio_rw_i2c1_data 176531532/* Register rw_i2c1_data2, scope gio, type rw */533typedef struct {534unsigned int data4 : 8;535unsigned int data5 : 8;536unsigned int start_val : 6;537unsigned int ack_val : 6;538unsigned int dummy1 : 4;539} reg_gio_rw_i2c1_data2;540#define REG_RD_ADDR_gio_rw_i2c1_data2 180541#define REG_WR_ADDR_gio_rw_i2c1_data2 180542543/* Register r_ppwm_stat, scope gio, type r */544typedef struct {545unsigned int freq : 2;546unsigned int dummy1 : 30;547} reg_gio_r_ppwm_stat;548#define REG_RD_ADDR_gio_r_ppwm_stat 184549550/* Register rw_ppwm_data, scope gio, type rw */551typedef struct {552unsigned int data : 8;553unsigned int dummy1 : 24;554} reg_gio_rw_ppwm_data;555#define REG_RD_ADDR_gio_rw_ppwm_data 188556#define REG_WR_ADDR_gio_rw_ppwm_data 188557558/* Register rw_pwm0_ctrl, scope gio, type rw */559typedef struct {560unsigned int mode : 2;561unsigned int ccd_override : 1;562unsigned int ccd_val : 1;563unsigned int dummy1 : 28;564} reg_gio_rw_pwm0_ctrl;565#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192566#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192567568/* Register rw_pwm0_var, scope gio, type rw */569typedef struct {570unsigned int lo : 13;571unsigned int hi : 13;572unsigned int dummy1 : 6;573} reg_gio_rw_pwm0_var;574#define REG_RD_ADDR_gio_rw_pwm0_var 196575#define REG_WR_ADDR_gio_rw_pwm0_var 196576577/* Register rw_pwm0_data, scope gio, type rw */578typedef struct {579unsigned int data : 8;580unsigned int dummy1 : 24;581} reg_gio_rw_pwm0_data;582#define REG_RD_ADDR_gio_rw_pwm0_data 200583#define REG_WR_ADDR_gio_rw_pwm0_data 200584585/* Register rw_pwm1_ctrl, scope gio, type rw */586typedef struct {587unsigned int mode : 2;588unsigned int ccd_override : 1;589unsigned int ccd_val : 1;590unsigned int dummy1 : 28;591} reg_gio_rw_pwm1_ctrl;592#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204593#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204594595/* Register rw_pwm1_var, scope gio, type rw */596typedef struct {597unsigned int lo : 13;598unsigned int hi : 13;599unsigned int dummy1 : 6;600} reg_gio_rw_pwm1_var;601#define REG_RD_ADDR_gio_rw_pwm1_var 208602#define REG_WR_ADDR_gio_rw_pwm1_var 208603604/* Register rw_pwm1_data, scope gio, type rw */605typedef struct {606unsigned int data : 8;607unsigned int dummy1 : 24;608} reg_gio_rw_pwm1_data;609#define REG_RD_ADDR_gio_rw_pwm1_data 212610#define REG_WR_ADDR_gio_rw_pwm1_data 212611612/* Register rw_pwm2_ctrl, scope gio, type rw */613typedef struct {614unsigned int mode : 2;615unsigned int ccd_override : 1;616unsigned int ccd_val : 1;617unsigned int dummy1 : 28;618} reg_gio_rw_pwm2_ctrl;619#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216620#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216621622/* Register rw_pwm2_var, scope gio, type rw */623typedef struct {624unsigned int lo : 13;625unsigned int hi : 13;626unsigned int dummy1 : 6;627} reg_gio_rw_pwm2_var;628#define REG_RD_ADDR_gio_rw_pwm2_var 220629#define REG_WR_ADDR_gio_rw_pwm2_var 220630631/* Register rw_pwm2_data, scope gio, type rw */632typedef struct {633unsigned int data : 8;634unsigned int dummy1 : 24;635} reg_gio_rw_pwm2_data;636#define REG_RD_ADDR_gio_rw_pwm2_data 224637#define REG_WR_ADDR_gio_rw_pwm2_data 224638639/* Register rw_pwm_in_cfg, scope gio, type rw */640typedef struct {641unsigned int pin : 3;642unsigned int dummy1 : 29;643} reg_gio_rw_pwm_in_cfg;644#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228645#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228646647/* Register r_pwm_in_lo, scope gio, type r */648typedef struct {649unsigned int data : 32;650} reg_gio_r_pwm_in_lo;651#define REG_RD_ADDR_gio_r_pwm_in_lo 232652653/* Register r_pwm_in_hi, scope gio, type r */654typedef struct {655unsigned int data : 32;656} reg_gio_r_pwm_in_hi;657#define REG_RD_ADDR_gio_r_pwm_in_hi 236658659/* Register r_pwm_in_cnt, scope gio, type r */660typedef struct {661unsigned int data : 32;662} reg_gio_r_pwm_in_cnt;663#define REG_RD_ADDR_gio_r_pwm_in_cnt 240664665666/* Constants */667enum {668regk_gio_anyedge = 0x00000007,669regk_gio_f100k = 0x00000000,670regk_gio_f1562 = 0x00000000,671regk_gio_f195 = 0x00000003,672regk_gio_f1m = 0x00000002,673regk_gio_f390 = 0x00000002,674regk_gio_f400k = 0x00000001,675regk_gio_f5m = 0x00000003,676regk_gio_f781 = 0x00000001,677regk_gio_hi = 0x00000001,678regk_gio_in = 0x00000000,679regk_gio_intr_pa0 = 0x00000000,680regk_gio_intr_pa1 = 0x00000000,681regk_gio_intr_pa10 = 0x00000001,682regk_gio_intr_pa11 = 0x00000001,683regk_gio_intr_pa12 = 0x00000001,684regk_gio_intr_pa13 = 0x00000001,685regk_gio_intr_pa14 = 0x00000001,686regk_gio_intr_pa15 = 0x00000001,687regk_gio_intr_pa16 = 0x00000002,688regk_gio_intr_pa17 = 0x00000002,689regk_gio_intr_pa18 = 0x00000002,690regk_gio_intr_pa19 = 0x00000002,691regk_gio_intr_pa2 = 0x00000000,692regk_gio_intr_pa20 = 0x00000002,693regk_gio_intr_pa21 = 0x00000002,694regk_gio_intr_pa22 = 0x00000002,695regk_gio_intr_pa23 = 0x00000002,696regk_gio_intr_pa24 = 0x00000003,697regk_gio_intr_pa25 = 0x00000003,698regk_gio_intr_pa26 = 0x00000003,699regk_gio_intr_pa27 = 0x00000003,700regk_gio_intr_pa28 = 0x00000003,701regk_gio_intr_pa29 = 0x00000003,702regk_gio_intr_pa3 = 0x00000000,703regk_gio_intr_pa30 = 0x00000003,704regk_gio_intr_pa31 = 0x00000003,705regk_gio_intr_pa4 = 0x00000000,706regk_gio_intr_pa5 = 0x00000000,707regk_gio_intr_pa6 = 0x00000000,708regk_gio_intr_pa7 = 0x00000000,709regk_gio_intr_pa8 = 0x00000001,710regk_gio_intr_pa9 = 0x00000001,711regk_gio_intr_pb0 = 0x00000004,712regk_gio_intr_pb1 = 0x00000004,713regk_gio_intr_pb10 = 0x00000005,714regk_gio_intr_pb11 = 0x00000005,715regk_gio_intr_pb12 = 0x00000005,716regk_gio_intr_pb13 = 0x00000005,717regk_gio_intr_pb14 = 0x00000005,718regk_gio_intr_pb15 = 0x00000005,719regk_gio_intr_pb16 = 0x00000006,720regk_gio_intr_pb17 = 0x00000006,721regk_gio_intr_pb18 = 0x00000006,722regk_gio_intr_pb19 = 0x00000006,723regk_gio_intr_pb2 = 0x00000004,724regk_gio_intr_pb20 = 0x00000006,725regk_gio_intr_pb21 = 0x00000006,726regk_gio_intr_pb22 = 0x00000006,727regk_gio_intr_pb23 = 0x00000006,728regk_gio_intr_pb24 = 0x00000007,729regk_gio_intr_pb25 = 0x00000007,730regk_gio_intr_pb26 = 0x00000007,731regk_gio_intr_pb27 = 0x00000007,732regk_gio_intr_pb28 = 0x00000007,733regk_gio_intr_pb29 = 0x00000007,734regk_gio_intr_pb3 = 0x00000004,735regk_gio_intr_pb30 = 0x00000007,736regk_gio_intr_pb31 = 0x00000007,737regk_gio_intr_pb4 = 0x00000004,738regk_gio_intr_pb5 = 0x00000004,739regk_gio_intr_pb6 = 0x00000004,740regk_gio_intr_pb7 = 0x00000004,741regk_gio_intr_pb8 = 0x00000005,742regk_gio_intr_pb9 = 0x00000005,743regk_gio_intr_pc0 = 0x00000008,744regk_gio_intr_pc1 = 0x00000008,745regk_gio_intr_pc10 = 0x00000009,746regk_gio_intr_pc11 = 0x00000009,747regk_gio_intr_pc12 = 0x00000009,748regk_gio_intr_pc13 = 0x00000009,749regk_gio_intr_pc14 = 0x00000009,750regk_gio_intr_pc15 = 0x00000009,751regk_gio_intr_pc2 = 0x00000008,752regk_gio_intr_pc3 = 0x00000008,753regk_gio_intr_pc4 = 0x00000008,754regk_gio_intr_pc5 = 0x00000008,755regk_gio_intr_pc6 = 0x00000008,756regk_gio_intr_pc7 = 0x00000008,757regk_gio_intr_pc8 = 0x00000009,758regk_gio_intr_pc9 = 0x00000009,759regk_gio_intr_pd0 = 0x0000000c,760regk_gio_intr_pd1 = 0x0000000c,761regk_gio_intr_pd10 = 0x0000000d,762regk_gio_intr_pd11 = 0x0000000d,763regk_gio_intr_pd12 = 0x0000000d,764regk_gio_intr_pd13 = 0x0000000d,765regk_gio_intr_pd14 = 0x0000000d,766regk_gio_intr_pd15 = 0x0000000d,767regk_gio_intr_pd16 = 0x0000000e,768regk_gio_intr_pd17 = 0x0000000e,769regk_gio_intr_pd18 = 0x0000000e,770regk_gio_intr_pd19 = 0x0000000e,771regk_gio_intr_pd2 = 0x0000000c,772regk_gio_intr_pd20 = 0x0000000e,773regk_gio_intr_pd21 = 0x0000000e,774regk_gio_intr_pd22 = 0x0000000e,775regk_gio_intr_pd23 = 0x0000000e,776regk_gio_intr_pd24 = 0x0000000f,777regk_gio_intr_pd25 = 0x0000000f,778regk_gio_intr_pd26 = 0x0000000f,779regk_gio_intr_pd27 = 0x0000000f,780regk_gio_intr_pd28 = 0x0000000f,781regk_gio_intr_pd29 = 0x0000000f,782regk_gio_intr_pd3 = 0x0000000c,783regk_gio_intr_pd30 = 0x0000000f,784regk_gio_intr_pd31 = 0x0000000f,785regk_gio_intr_pd4 = 0x0000000c,786regk_gio_intr_pd5 = 0x0000000c,787regk_gio_intr_pd6 = 0x0000000c,788regk_gio_intr_pd7 = 0x0000000c,789regk_gio_intr_pd8 = 0x0000000d,790regk_gio_intr_pd9 = 0x0000000d,791regk_gio_lo = 0x00000002,792regk_gio_lsb = 0x00000000,793regk_gio_msb = 0x00000001,794regk_gio_negedge = 0x00000006,795regk_gio_no = 0x00000000,796regk_gio_no_switch = 0x0000003f,797regk_gio_none = 0x00000007,798regk_gio_off = 0x00000000,799regk_gio_opendrain = 0x00000000,800regk_gio_out = 0x00000001,801regk_gio_posedge = 0x00000005,802regk_gio_pwm_hfp = 0x00000002,803regk_gio_pwm_pa0 = 0x00000001,804regk_gio_pwm_pa19 = 0x00000004,805regk_gio_pwm_pa6 = 0x00000002,806regk_gio_pwm_pa7 = 0x00000003,807regk_gio_pwm_pb26 = 0x00000005,808regk_gio_pwm_pd23 = 0x00000006,809regk_gio_pwm_pd31 = 0x00000007,810regk_gio_pwm_std = 0x00000001,811regk_gio_pwm_var = 0x00000003,812regk_gio_rw_i2c0_cfg_default = 0x00000020,813regk_gio_rw_i2c0_ctrl_default = 0x00010000,814regk_gio_rw_i2c0_start_default = 0x00000000,815regk_gio_rw_i2c1_cfg_default = 0x00000aa0,816regk_gio_rw_i2c1_ctrl_default = 0x00010000,817regk_gio_rw_i2c1_start_default = 0x00000000,818regk_gio_rw_intr_cfg_default = 0x00000000,819regk_gio_rw_intr_mask_default = 0x00000000,820regk_gio_rw_pa_oe_default = 0x00000000,821regk_gio_rw_pb_oe_default = 0x00000000,822regk_gio_rw_pc_oe_default = 0x00000000,823regk_gio_rw_ppwm_data_default = 0x00000000,824regk_gio_rw_pwm0_ctrl_default = 0x00000000,825regk_gio_rw_pwm1_ctrl_default = 0x00000000,826regk_gio_rw_pwm2_ctrl_default = 0x00000000,827regk_gio_rw_pwm_in_cfg_default = 0x00000000,828regk_gio_sda0 = 0x00000000,829regk_gio_sda1 = 0x00000001,830regk_gio_sda2 = 0x00000002,831regk_gio_sda3 = 0x00000003,832regk_gio_sen = 0x00000000,833regk_gio_set = 0x00000003,834regk_gio_yes = 0x00000001835};836#endif /* __gio_defs_h */837838839