Path: blob/master/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h
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#ifndef __l2cache_defs_h1#define __l2cache_defs_h23/*4* This file is autogenerated from5* file: l2cache.r6*7* by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r8* Any changes here will be lost.9*10* -*- buffer-read-only: t -*-11*/12/* Main access macros */13#ifndef REG_RD14#define REG_RD( scope, inst, reg ) \15REG_READ( reg_##scope##_##reg, \16(inst) + REG_RD_ADDR_##scope##_##reg )17#endif1819#ifndef REG_WR20#define REG_WR( scope, inst, reg, val ) \21REG_WRITE( reg_##scope##_##reg, \22(inst) + REG_WR_ADDR_##scope##_##reg, (val) )23#endif2425#ifndef REG_RD_VECT26#define REG_RD_VECT( scope, inst, reg, index ) \27REG_READ( reg_##scope##_##reg, \28(inst) + REG_RD_ADDR_##scope##_##reg + \29(index) * STRIDE_##scope##_##reg )30#endif3132#ifndef REG_WR_VECT33#define REG_WR_VECT( scope, inst, reg, index, val ) \34REG_WRITE( reg_##scope##_##reg, \35(inst) + REG_WR_ADDR_##scope##_##reg + \36(index) * STRIDE_##scope##_##reg, (val) )37#endif3839#ifndef REG_RD_INT40#define REG_RD_INT( scope, inst, reg ) \41REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )42#endif4344#ifndef REG_WR_INT45#define REG_WR_INT( scope, inst, reg, val ) \46REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )47#endif4849#ifndef REG_RD_INT_VECT50#define REG_RD_INT_VECT( scope, inst, reg, index ) \51REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \52(index) * STRIDE_##scope##_##reg )53#endif5455#ifndef REG_WR_INT_VECT56#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \57REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \58(index) * STRIDE_##scope##_##reg, (val) )59#endif6061#ifndef REG_TYPE_CONV62#define REG_TYPE_CONV( type, orgtype, val ) \63( { union { orgtype o; type n; } r; r.o = val; r.n; } )64#endif6566#ifndef reg_page_size67#define reg_page_size 819268#endif6970#ifndef REG_ADDR71#define REG_ADDR( scope, inst, reg ) \72( (inst) + REG_RD_ADDR_##scope##_##reg )73#endif7475#ifndef REG_ADDR_VECT76#define REG_ADDR_VECT( scope, inst, reg, index ) \77( (inst) + REG_RD_ADDR_##scope##_##reg + \78(index) * STRIDE_##scope##_##reg )79#endif8081/* C-code for register scope l2cache */8283/* Register rw_cfg, scope l2cache, type rw */84typedef struct {85unsigned int en : 1;86unsigned int dummy1 : 31;87} reg_l2cache_rw_cfg;88#define REG_RD_ADDR_l2cache_rw_cfg 089#define REG_WR_ADDR_l2cache_rw_cfg 09091/* Register rw_ctrl, scope l2cache, type rw */92typedef struct {93unsigned int dummy1 : 7;94unsigned int cbase : 9;95unsigned int dummy2 : 4;96unsigned int csize : 10;97unsigned int dummy3 : 2;98} reg_l2cache_rw_ctrl;99#define REG_RD_ADDR_l2cache_rw_ctrl 4100#define REG_WR_ADDR_l2cache_rw_ctrl 4101102/* Register rw_idxop, scope l2cache, type rw */103typedef struct {104unsigned int idx : 10;105unsigned int dummy1 : 14;106unsigned int way : 3;107unsigned int dummy2 : 2;108unsigned int cmd : 3;109} reg_l2cache_rw_idxop;110#define REG_RD_ADDR_l2cache_rw_idxop 8111#define REG_WR_ADDR_l2cache_rw_idxop 8112113/* Register rw_addrop_addr, scope l2cache, type rw */114typedef struct {115unsigned int addr : 32;116} reg_l2cache_rw_addrop_addr;117#define REG_RD_ADDR_l2cache_rw_addrop_addr 12118#define REG_WR_ADDR_l2cache_rw_addrop_addr 12119120/* Register rw_addrop_ctrl, scope l2cache, type rw */121typedef struct {122unsigned int size : 16;123unsigned int dummy1 : 13;124unsigned int cmd : 3;125} reg_l2cache_rw_addrop_ctrl;126#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16127#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16128129130/* Constants */131enum {132regk_l2cache_flush = 0x00000001,133regk_l2cache_no = 0x00000000,134regk_l2cache_rw_addrop_addr_default = 0x00000000,135regk_l2cache_rw_addrop_ctrl_default = 0x00000000,136regk_l2cache_rw_cfg_default = 0x00000000,137regk_l2cache_rw_ctrl_default = 0x00000000,138regk_l2cache_rw_idxop_default = 0x00000000,139regk_l2cache_yes = 0x00000001140};141#endif /* __l2cache_defs_h */142143144