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awilliam
GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h
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#ifndef __l2cache_defs_h
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#define __l2cache_defs_h
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/*
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* This file is autogenerated from
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* file: l2cache.r
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*
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* by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope l2cache */
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/* Register rw_cfg, scope l2cache, type rw */
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typedef struct {
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unsigned int en : 1;
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unsigned int dummy1 : 31;
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} reg_l2cache_rw_cfg;
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#define REG_RD_ADDR_l2cache_rw_cfg 0
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#define REG_WR_ADDR_l2cache_rw_cfg 0
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/* Register rw_ctrl, scope l2cache, type rw */
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typedef struct {
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unsigned int dummy1 : 7;
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unsigned int cbase : 9;
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unsigned int dummy2 : 4;
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unsigned int csize : 10;
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unsigned int dummy3 : 2;
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} reg_l2cache_rw_ctrl;
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#define REG_RD_ADDR_l2cache_rw_ctrl 4
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#define REG_WR_ADDR_l2cache_rw_ctrl 4
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/* Register rw_idxop, scope l2cache, type rw */
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typedef struct {
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unsigned int idx : 10;
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unsigned int dummy1 : 14;
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unsigned int way : 3;
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unsigned int dummy2 : 2;
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unsigned int cmd : 3;
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} reg_l2cache_rw_idxop;
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#define REG_RD_ADDR_l2cache_rw_idxop 8
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#define REG_WR_ADDR_l2cache_rw_idxop 8
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/* Register rw_addrop_addr, scope l2cache, type rw */
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typedef struct {
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unsigned int addr : 32;
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} reg_l2cache_rw_addrop_addr;
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#define REG_RD_ADDR_l2cache_rw_addrop_addr 12
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#define REG_WR_ADDR_l2cache_rw_addrop_addr 12
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/* Register rw_addrop_ctrl, scope l2cache, type rw */
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typedef struct {
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unsigned int size : 16;
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unsigned int dummy1 : 13;
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unsigned int cmd : 3;
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} reg_l2cache_rw_addrop_ctrl;
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#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
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#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
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/* Constants */
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enum {
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regk_l2cache_flush = 0x00000001,
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regk_l2cache_no = 0x00000000,
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regk_l2cache_rw_addrop_addr_default = 0x00000000,
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regk_l2cache_rw_addrop_ctrl_default = 0x00000000,
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regk_l2cache_rw_cfg_default = 0x00000000,
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regk_l2cache_rw_ctrl_default = 0x00000000,
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regk_l2cache_rw_idxop_default = 0x00000000,
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regk_l2cache_yes = 0x00000001
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};
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#endif /* __l2cache_defs_h */
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