Path: blob/master/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h
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#ifndef __gio_defs_h1#define __gio_defs_h23/*4* This file is autogenerated from5* file: ../../inst/gio/rtl/gio_regs.r6* id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp7* last modfied: Mon Apr 11 16:07:47 20058*9* by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r10* id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $11* Any changes here will be lost.12*13* -*- buffer-read-only: t -*-14*/15/* Main access macros */16#ifndef REG_RD17#define REG_RD( scope, inst, reg ) \18REG_READ( reg_##scope##_##reg, \19(inst) + REG_RD_ADDR_##scope##_##reg )20#endif2122#ifndef REG_WR23#define REG_WR( scope, inst, reg, val ) \24REG_WRITE( reg_##scope##_##reg, \25(inst) + REG_WR_ADDR_##scope##_##reg, (val) )26#endif2728#ifndef REG_RD_VECT29#define REG_RD_VECT( scope, inst, reg, index ) \30REG_READ( reg_##scope##_##reg, \31(inst) + REG_RD_ADDR_##scope##_##reg + \32(index) * STRIDE_##scope##_##reg )33#endif3435#ifndef REG_WR_VECT36#define REG_WR_VECT( scope, inst, reg, index, val ) \37REG_WRITE( reg_##scope##_##reg, \38(inst) + REG_WR_ADDR_##scope##_##reg + \39(index) * STRIDE_##scope##_##reg, (val) )40#endif4142#ifndef REG_RD_INT43#define REG_RD_INT( scope, inst, reg ) \44REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )45#endif4647#ifndef REG_WR_INT48#define REG_WR_INT( scope, inst, reg, val ) \49REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )50#endif5152#ifndef REG_RD_INT_VECT53#define REG_RD_INT_VECT( scope, inst, reg, index ) \54REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \55(index) * STRIDE_##scope##_##reg )56#endif5758#ifndef REG_WR_INT_VECT59#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \60REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \61(index) * STRIDE_##scope##_##reg, (val) )62#endif6364#ifndef REG_TYPE_CONV65#define REG_TYPE_CONV( type, orgtype, val ) \66( { union { orgtype o; type n; } r; r.o = val; r.n; } )67#endif6869#ifndef reg_page_size70#define reg_page_size 819271#endif7273#ifndef REG_ADDR74#define REG_ADDR( scope, inst, reg ) \75( (inst) + REG_RD_ADDR_##scope##_##reg )76#endif7778#ifndef REG_ADDR_VECT79#define REG_ADDR_VECT( scope, inst, reg, index ) \80( (inst) + REG_RD_ADDR_##scope##_##reg + \81(index) * STRIDE_##scope##_##reg )82#endif8384/* C-code for register scope gio */8586/* Register rw_pa_dout, scope gio, type rw */87typedef struct {88unsigned int data : 8;89unsigned int dummy1 : 24;90} reg_gio_rw_pa_dout;91#define REG_RD_ADDR_gio_rw_pa_dout 092#define REG_WR_ADDR_gio_rw_pa_dout 09394/* Register r_pa_din, scope gio, type r */95typedef struct {96unsigned int data : 8;97unsigned int dummy1 : 24;98} reg_gio_r_pa_din;99#define REG_RD_ADDR_gio_r_pa_din 4100101/* Register rw_pa_oe, scope gio, type rw */102typedef struct {103unsigned int oe : 8;104unsigned int dummy1 : 24;105} reg_gio_rw_pa_oe;106#define REG_RD_ADDR_gio_rw_pa_oe 8107#define REG_WR_ADDR_gio_rw_pa_oe 8108109/* Register rw_intr_cfg, scope gio, type rw */110typedef struct {111unsigned int pa0 : 3;112unsigned int pa1 : 3;113unsigned int pa2 : 3;114unsigned int pa3 : 3;115unsigned int pa4 : 3;116unsigned int pa5 : 3;117unsigned int pa6 : 3;118unsigned int pa7 : 3;119unsigned int dummy1 : 8;120} reg_gio_rw_intr_cfg;121#define REG_RD_ADDR_gio_rw_intr_cfg 12122#define REG_WR_ADDR_gio_rw_intr_cfg 12123124/* Register rw_intr_mask, scope gio, type rw */125typedef struct {126unsigned int pa0 : 1;127unsigned int pa1 : 1;128unsigned int pa2 : 1;129unsigned int pa3 : 1;130unsigned int pa4 : 1;131unsigned int pa5 : 1;132unsigned int pa6 : 1;133unsigned int pa7 : 1;134unsigned int dummy1 : 24;135} reg_gio_rw_intr_mask;136#define REG_RD_ADDR_gio_rw_intr_mask 16137#define REG_WR_ADDR_gio_rw_intr_mask 16138139/* Register rw_ack_intr, scope gio, type rw */140typedef struct {141unsigned int pa0 : 1;142unsigned int pa1 : 1;143unsigned int pa2 : 1;144unsigned int pa3 : 1;145unsigned int pa4 : 1;146unsigned int pa5 : 1;147unsigned int pa6 : 1;148unsigned int pa7 : 1;149unsigned int dummy1 : 24;150} reg_gio_rw_ack_intr;151#define REG_RD_ADDR_gio_rw_ack_intr 20152#define REG_WR_ADDR_gio_rw_ack_intr 20153154/* Register r_intr, scope gio, type r */155typedef struct {156unsigned int pa0 : 1;157unsigned int pa1 : 1;158unsigned int pa2 : 1;159unsigned int pa3 : 1;160unsigned int pa4 : 1;161unsigned int pa5 : 1;162unsigned int pa6 : 1;163unsigned int pa7 : 1;164unsigned int dummy1 : 24;165} reg_gio_r_intr;166#define REG_RD_ADDR_gio_r_intr 24167168/* Register r_masked_intr, scope gio, type r */169typedef struct {170unsigned int pa0 : 1;171unsigned int pa1 : 1;172unsigned int pa2 : 1;173unsigned int pa3 : 1;174unsigned int pa4 : 1;175unsigned int pa5 : 1;176unsigned int pa6 : 1;177unsigned int pa7 : 1;178unsigned int dummy1 : 24;179} reg_gio_r_masked_intr;180#define REG_RD_ADDR_gio_r_masked_intr 28181182/* Register rw_pb_dout, scope gio, type rw */183typedef struct {184unsigned int data : 18;185unsigned int dummy1 : 14;186} reg_gio_rw_pb_dout;187#define REG_RD_ADDR_gio_rw_pb_dout 32188#define REG_WR_ADDR_gio_rw_pb_dout 32189190/* Register r_pb_din, scope gio, type r */191typedef struct {192unsigned int data : 18;193unsigned int dummy1 : 14;194} reg_gio_r_pb_din;195#define REG_RD_ADDR_gio_r_pb_din 36196197/* Register rw_pb_oe, scope gio, type rw */198typedef struct {199unsigned int oe : 18;200unsigned int dummy1 : 14;201} reg_gio_rw_pb_oe;202#define REG_RD_ADDR_gio_rw_pb_oe 40203#define REG_WR_ADDR_gio_rw_pb_oe 40204205/* Register rw_pc_dout, scope gio, type rw */206typedef struct {207unsigned int data : 18;208unsigned int dummy1 : 14;209} reg_gio_rw_pc_dout;210#define REG_RD_ADDR_gio_rw_pc_dout 48211#define REG_WR_ADDR_gio_rw_pc_dout 48212213/* Register r_pc_din, scope gio, type r */214typedef struct {215unsigned int data : 18;216unsigned int dummy1 : 14;217} reg_gio_r_pc_din;218#define REG_RD_ADDR_gio_r_pc_din 52219220/* Register rw_pc_oe, scope gio, type rw */221typedef struct {222unsigned int oe : 18;223unsigned int dummy1 : 14;224} reg_gio_rw_pc_oe;225#define REG_RD_ADDR_gio_rw_pc_oe 56226#define REG_WR_ADDR_gio_rw_pc_oe 56227228/* Register rw_pd_dout, scope gio, type rw */229typedef struct {230unsigned int data : 18;231unsigned int dummy1 : 14;232} reg_gio_rw_pd_dout;233#define REG_RD_ADDR_gio_rw_pd_dout 64234#define REG_WR_ADDR_gio_rw_pd_dout 64235236/* Register r_pd_din, scope gio, type r */237typedef struct {238unsigned int data : 18;239unsigned int dummy1 : 14;240} reg_gio_r_pd_din;241#define REG_RD_ADDR_gio_r_pd_din 68242243/* Register rw_pd_oe, scope gio, type rw */244typedef struct {245unsigned int oe : 18;246unsigned int dummy1 : 14;247} reg_gio_rw_pd_oe;248#define REG_RD_ADDR_gio_rw_pd_oe 72249#define REG_WR_ADDR_gio_rw_pd_oe 72250251/* Register rw_pe_dout, scope gio, type rw */252typedef struct {253unsigned int data : 18;254unsigned int dummy1 : 14;255} reg_gio_rw_pe_dout;256#define REG_RD_ADDR_gio_rw_pe_dout 80257#define REG_WR_ADDR_gio_rw_pe_dout 80258259/* Register r_pe_din, scope gio, type r */260typedef struct {261unsigned int data : 18;262unsigned int dummy1 : 14;263} reg_gio_r_pe_din;264#define REG_RD_ADDR_gio_r_pe_din 84265266/* Register rw_pe_oe, scope gio, type rw */267typedef struct {268unsigned int oe : 18;269unsigned int dummy1 : 14;270} reg_gio_rw_pe_oe;271#define REG_RD_ADDR_gio_rw_pe_oe 88272#define REG_WR_ADDR_gio_rw_pe_oe 88273274275/* Constants */276enum {277regk_gio_anyedge = 0x00000007,278regk_gio_hi = 0x00000001,279regk_gio_lo = 0x00000002,280regk_gio_negedge = 0x00000006,281regk_gio_no = 0x00000000,282regk_gio_off = 0x00000000,283regk_gio_posedge = 0x00000005,284regk_gio_rw_intr_cfg_default = 0x00000000,285regk_gio_rw_intr_mask_default = 0x00000000,286regk_gio_rw_pa_oe_default = 0x00000000,287regk_gio_rw_pb_oe_default = 0x00000000,288regk_gio_rw_pc_oe_default = 0x00000000,289regk_gio_rw_pd_oe_default = 0x00000000,290regk_gio_rw_pe_oe_default = 0x00000000,291regk_gio_set = 0x00000003,292regk_gio_yes = 0x00000001293};294#endif /* __gio_defs_h */295296297