Path: blob/master/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h
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/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version1from ../../inst/intr_vect/rtl/guinness/ivmask.config.r2version . */34#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R5#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R6#define MEMARB_INTR_VECT 0x317#define GEN_IO_INTR_VECT 0x328#define GIO_INTR_VECT GEN_IO_INTR_VECT9#define IOP0_INTR_VECT 0x3310#define IOP1_INTR_VECT 0x3411#define IOP2_INTR_VECT 0x3512#define IOP3_INTR_VECT 0x3613#define DMA0_INTR_VECT 0x3714#define DMA1_INTR_VECT 0x3815#define DMA2_INTR_VECT 0x3916#define DMA3_INTR_VECT 0x3a17#define DMA4_INTR_VECT 0x3b18#define DMA5_INTR_VECT 0x3c19#define DMA6_INTR_VECT 0x3d20#define DMA7_INTR_VECT 0x3e21#define DMA8_INTR_VECT 0x3f22#define DMA9_INTR_VECT 0x4023#define ATA_INTR_VECT 0x4124#define SSER0_INTR_VECT 0x4225#define SSER1_INTR_VECT 0x4326#define SER0_INTR_VECT 0x4427#define SER1_INTR_VECT 0x4528#define SER2_INTR_VECT 0x4629#define SER3_INTR_VECT 0x4730#define P21_INTR_VECT 0x4831#define ETH0_INTR_VECT 0x4932#define ETH1_INTR_VECT 0x4a33#define TIMER_INTR_VECT 0x4b34#define TIMER0_INTR_VECT TIMER_INTR_VECT35#define BIF_ARB_INTR_VECT 0x4c36#define BIF_DMA_INTR_VECT 0x4d37#define EXT_INTR_VECT 0x4e38#define IPI_INTR_VECT 0x4f39#define NBR_INTR_VECT 0x5040#endif414243