Path: blob/master/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h
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#ifndef __pinmux_defs_h1#define __pinmux_defs_h23/*4* This file is autogenerated from5* file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r6* id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp7* last modfied: Mon Apr 11 16:09:11 20058*9* by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r10* id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $11* Any changes here will be lost.12*13* -*- buffer-read-only: t -*-14*/15/* Main access macros */16#ifndef REG_RD17#define REG_RD( scope, inst, reg ) \18REG_READ( reg_##scope##_##reg, \19(inst) + REG_RD_ADDR_##scope##_##reg )20#endif2122#ifndef REG_WR23#define REG_WR( scope, inst, reg, val ) \24REG_WRITE( reg_##scope##_##reg, \25(inst) + REG_WR_ADDR_##scope##_##reg, (val) )26#endif2728#ifndef REG_RD_VECT29#define REG_RD_VECT( scope, inst, reg, index ) \30REG_READ( reg_##scope##_##reg, \31(inst) + REG_RD_ADDR_##scope##_##reg + \32(index) * STRIDE_##scope##_##reg )33#endif3435#ifndef REG_WR_VECT36#define REG_WR_VECT( scope, inst, reg, index, val ) \37REG_WRITE( reg_##scope##_##reg, \38(inst) + REG_WR_ADDR_##scope##_##reg + \39(index) * STRIDE_##scope##_##reg, (val) )40#endif4142#ifndef REG_RD_INT43#define REG_RD_INT( scope, inst, reg ) \44REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )45#endif4647#ifndef REG_WR_INT48#define REG_WR_INT( scope, inst, reg, val ) \49REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )50#endif5152#ifndef REG_RD_INT_VECT53#define REG_RD_INT_VECT( scope, inst, reg, index ) \54REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \55(index) * STRIDE_##scope##_##reg )56#endif5758#ifndef REG_WR_INT_VECT59#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \60REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \61(index) * STRIDE_##scope##_##reg, (val) )62#endif6364#ifndef REG_TYPE_CONV65#define REG_TYPE_CONV( type, orgtype, val ) \66( { union { orgtype o; type n; } r; r.o = val; r.n; } )67#endif6869#ifndef reg_page_size70#define reg_page_size 819271#endif7273#ifndef REG_ADDR74#define REG_ADDR( scope, inst, reg ) \75( (inst) + REG_RD_ADDR_##scope##_##reg )76#endif7778#ifndef REG_ADDR_VECT79#define REG_ADDR_VECT( scope, inst, reg, index ) \80( (inst) + REG_RD_ADDR_##scope##_##reg + \81(index) * STRIDE_##scope##_##reg )82#endif8384/* C-code for register scope pinmux */8586/* Register rw_pa, scope pinmux, type rw */87typedef struct {88unsigned int pa0 : 1;89unsigned int pa1 : 1;90unsigned int pa2 : 1;91unsigned int pa3 : 1;92unsigned int pa4 : 1;93unsigned int pa5 : 1;94unsigned int pa6 : 1;95unsigned int pa7 : 1;96unsigned int csp2_n : 1;97unsigned int csp3_n : 1;98unsigned int csp5_n : 1;99unsigned int csp6_n : 1;100unsigned int hsh4 : 1;101unsigned int hsh5 : 1;102unsigned int hsh6 : 1;103unsigned int hsh7 : 1;104unsigned int dummy1 : 16;105} reg_pinmux_rw_pa;106#define REG_RD_ADDR_pinmux_rw_pa 0107#define REG_WR_ADDR_pinmux_rw_pa 0108109/* Register rw_hwprot, scope pinmux, type rw */110typedef struct {111unsigned int ser1 : 1;112unsigned int ser2 : 1;113unsigned int ser3 : 1;114unsigned int sser0 : 1;115unsigned int sser1 : 1;116unsigned int ata0 : 1;117unsigned int ata1 : 1;118unsigned int ata2 : 1;119unsigned int ata3 : 1;120unsigned int ata : 1;121unsigned int eth1 : 1;122unsigned int eth1_mgm : 1;123unsigned int timer : 1;124unsigned int p21 : 1;125unsigned int dummy1 : 18;126} reg_pinmux_rw_hwprot;127#define REG_RD_ADDR_pinmux_rw_hwprot 4128#define REG_WR_ADDR_pinmux_rw_hwprot 4129130/* Register rw_pb_gio, scope pinmux, type rw */131typedef struct {132unsigned int pb0 : 1;133unsigned int pb1 : 1;134unsigned int pb2 : 1;135unsigned int pb3 : 1;136unsigned int pb4 : 1;137unsigned int pb5 : 1;138unsigned int pb6 : 1;139unsigned int pb7 : 1;140unsigned int pb8 : 1;141unsigned int pb9 : 1;142unsigned int pb10 : 1;143unsigned int pb11 : 1;144unsigned int pb12 : 1;145unsigned int pb13 : 1;146unsigned int pb14 : 1;147unsigned int pb15 : 1;148unsigned int pb16 : 1;149unsigned int pb17 : 1;150unsigned int dummy1 : 14;151} reg_pinmux_rw_pb_gio;152#define REG_RD_ADDR_pinmux_rw_pb_gio 8153#define REG_WR_ADDR_pinmux_rw_pb_gio 8154155/* Register rw_pb_iop, scope pinmux, type rw */156typedef struct {157unsigned int pb0 : 1;158unsigned int pb1 : 1;159unsigned int pb2 : 1;160unsigned int pb3 : 1;161unsigned int pb4 : 1;162unsigned int pb5 : 1;163unsigned int pb6 : 1;164unsigned int pb7 : 1;165unsigned int pb8 : 1;166unsigned int pb9 : 1;167unsigned int pb10 : 1;168unsigned int pb11 : 1;169unsigned int pb12 : 1;170unsigned int pb13 : 1;171unsigned int pb14 : 1;172unsigned int pb15 : 1;173unsigned int pb16 : 1;174unsigned int pb17 : 1;175unsigned int dummy1 : 14;176} reg_pinmux_rw_pb_iop;177#define REG_RD_ADDR_pinmux_rw_pb_iop 12178#define REG_WR_ADDR_pinmux_rw_pb_iop 12179180/* Register rw_pc_gio, scope pinmux, type rw */181typedef struct {182unsigned int pc0 : 1;183unsigned int pc1 : 1;184unsigned int pc2 : 1;185unsigned int pc3 : 1;186unsigned int pc4 : 1;187unsigned int pc5 : 1;188unsigned int pc6 : 1;189unsigned int pc7 : 1;190unsigned int pc8 : 1;191unsigned int pc9 : 1;192unsigned int pc10 : 1;193unsigned int pc11 : 1;194unsigned int pc12 : 1;195unsigned int pc13 : 1;196unsigned int pc14 : 1;197unsigned int pc15 : 1;198unsigned int pc16 : 1;199unsigned int pc17 : 1;200unsigned int dummy1 : 14;201} reg_pinmux_rw_pc_gio;202#define REG_RD_ADDR_pinmux_rw_pc_gio 16203#define REG_WR_ADDR_pinmux_rw_pc_gio 16204205/* Register rw_pc_iop, scope pinmux, type rw */206typedef struct {207unsigned int pc0 : 1;208unsigned int pc1 : 1;209unsigned int pc2 : 1;210unsigned int pc3 : 1;211unsigned int pc4 : 1;212unsigned int pc5 : 1;213unsigned int pc6 : 1;214unsigned int pc7 : 1;215unsigned int pc8 : 1;216unsigned int pc9 : 1;217unsigned int pc10 : 1;218unsigned int pc11 : 1;219unsigned int pc12 : 1;220unsigned int pc13 : 1;221unsigned int pc14 : 1;222unsigned int pc15 : 1;223unsigned int pc16 : 1;224unsigned int pc17 : 1;225unsigned int dummy1 : 14;226} reg_pinmux_rw_pc_iop;227#define REG_RD_ADDR_pinmux_rw_pc_iop 20228#define REG_WR_ADDR_pinmux_rw_pc_iop 20229230/* Register rw_pd_gio, scope pinmux, type rw */231typedef struct {232unsigned int pd0 : 1;233unsigned int pd1 : 1;234unsigned int pd2 : 1;235unsigned int pd3 : 1;236unsigned int pd4 : 1;237unsigned int pd5 : 1;238unsigned int pd6 : 1;239unsigned int pd7 : 1;240unsigned int pd8 : 1;241unsigned int pd9 : 1;242unsigned int pd10 : 1;243unsigned int pd11 : 1;244unsigned int pd12 : 1;245unsigned int pd13 : 1;246unsigned int pd14 : 1;247unsigned int pd15 : 1;248unsigned int pd16 : 1;249unsigned int pd17 : 1;250unsigned int dummy1 : 14;251} reg_pinmux_rw_pd_gio;252#define REG_RD_ADDR_pinmux_rw_pd_gio 24253#define REG_WR_ADDR_pinmux_rw_pd_gio 24254255/* Register rw_pd_iop, scope pinmux, type rw */256typedef struct {257unsigned int pd0 : 1;258unsigned int pd1 : 1;259unsigned int pd2 : 1;260unsigned int pd3 : 1;261unsigned int pd4 : 1;262unsigned int pd5 : 1;263unsigned int pd6 : 1;264unsigned int pd7 : 1;265unsigned int pd8 : 1;266unsigned int pd9 : 1;267unsigned int pd10 : 1;268unsigned int pd11 : 1;269unsigned int pd12 : 1;270unsigned int pd13 : 1;271unsigned int pd14 : 1;272unsigned int pd15 : 1;273unsigned int pd16 : 1;274unsigned int pd17 : 1;275unsigned int dummy1 : 14;276} reg_pinmux_rw_pd_iop;277#define REG_RD_ADDR_pinmux_rw_pd_iop 28278#define REG_WR_ADDR_pinmux_rw_pd_iop 28279280/* Register rw_pe_gio, scope pinmux, type rw */281typedef struct {282unsigned int pe0 : 1;283unsigned int pe1 : 1;284unsigned int pe2 : 1;285unsigned int pe3 : 1;286unsigned int pe4 : 1;287unsigned int pe5 : 1;288unsigned int pe6 : 1;289unsigned int pe7 : 1;290unsigned int pe8 : 1;291unsigned int pe9 : 1;292unsigned int pe10 : 1;293unsigned int pe11 : 1;294unsigned int pe12 : 1;295unsigned int pe13 : 1;296unsigned int pe14 : 1;297unsigned int pe15 : 1;298unsigned int pe16 : 1;299unsigned int pe17 : 1;300unsigned int dummy1 : 14;301} reg_pinmux_rw_pe_gio;302#define REG_RD_ADDR_pinmux_rw_pe_gio 32303#define REG_WR_ADDR_pinmux_rw_pe_gio 32304305/* Register rw_pe_iop, scope pinmux, type rw */306typedef struct {307unsigned int pe0 : 1;308unsigned int pe1 : 1;309unsigned int pe2 : 1;310unsigned int pe3 : 1;311unsigned int pe4 : 1;312unsigned int pe5 : 1;313unsigned int pe6 : 1;314unsigned int pe7 : 1;315unsigned int pe8 : 1;316unsigned int pe9 : 1;317unsigned int pe10 : 1;318unsigned int pe11 : 1;319unsigned int pe12 : 1;320unsigned int pe13 : 1;321unsigned int pe14 : 1;322unsigned int pe15 : 1;323unsigned int pe16 : 1;324unsigned int pe17 : 1;325unsigned int dummy1 : 14;326} reg_pinmux_rw_pe_iop;327#define REG_RD_ADDR_pinmux_rw_pe_iop 36328#define REG_WR_ADDR_pinmux_rw_pe_iop 36329330/* Register rw_usb_phy, scope pinmux, type rw */331typedef struct {332unsigned int en_usb0 : 1;333unsigned int en_usb1 : 1;334unsigned int dummy1 : 30;335} reg_pinmux_rw_usb_phy;336#define REG_RD_ADDR_pinmux_rw_usb_phy 40337#define REG_WR_ADDR_pinmux_rw_usb_phy 40338339340/* Constants */341enum {342regk_pinmux_no = 0x00000000,343regk_pinmux_rw_hwprot_default = 0x00000000,344regk_pinmux_rw_pa_default = 0x00000000,345regk_pinmux_rw_pb_gio_default = 0x00000000,346regk_pinmux_rw_pb_iop_default = 0x00000000,347regk_pinmux_rw_pc_gio_default = 0x00000000,348regk_pinmux_rw_pc_iop_default = 0x00000000,349regk_pinmux_rw_pd_gio_default = 0x00000000,350regk_pinmux_rw_pd_iop_default = 0x00000000,351regk_pinmux_rw_pe_gio_default = 0x00000000,352regk_pinmux_rw_pe_iop_default = 0x00000000,353regk_pinmux_rw_usb_phy_default = 0x00000000,354regk_pinmux_yes = 0x00000001355};356#endif /* __pinmux_defs_h */357358359