Path: blob/master/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h
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#ifndef __strmux_defs_h1#define __strmux_defs_h23/*4* This file is autogenerated from5* file: ../../inst/strmux/rtl/guinness/strmux_regs.r6* id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp7* last modfied: Mon Apr 11 16:09:43 20058*9* by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r10* id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $11* Any changes here will be lost.12*13* -*- buffer-read-only: t -*-14*/15/* Main access macros */16#ifndef REG_RD17#define REG_RD( scope, inst, reg ) \18REG_READ( reg_##scope##_##reg, \19(inst) + REG_RD_ADDR_##scope##_##reg )20#endif2122#ifndef REG_WR23#define REG_WR( scope, inst, reg, val ) \24REG_WRITE( reg_##scope##_##reg, \25(inst) + REG_WR_ADDR_##scope##_##reg, (val) )26#endif2728#ifndef REG_RD_VECT29#define REG_RD_VECT( scope, inst, reg, index ) \30REG_READ( reg_##scope##_##reg, \31(inst) + REG_RD_ADDR_##scope##_##reg + \32(index) * STRIDE_##scope##_##reg )33#endif3435#ifndef REG_WR_VECT36#define REG_WR_VECT( scope, inst, reg, index, val ) \37REG_WRITE( reg_##scope##_##reg, \38(inst) + REG_WR_ADDR_##scope##_##reg + \39(index) * STRIDE_##scope##_##reg, (val) )40#endif4142#ifndef REG_RD_INT43#define REG_RD_INT( scope, inst, reg ) \44REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )45#endif4647#ifndef REG_WR_INT48#define REG_WR_INT( scope, inst, reg, val ) \49REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )50#endif5152#ifndef REG_RD_INT_VECT53#define REG_RD_INT_VECT( scope, inst, reg, index ) \54REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \55(index) * STRIDE_##scope##_##reg )56#endif5758#ifndef REG_WR_INT_VECT59#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \60REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \61(index) * STRIDE_##scope##_##reg, (val) )62#endif6364#ifndef REG_TYPE_CONV65#define REG_TYPE_CONV( type, orgtype, val ) \66( { union { orgtype o; type n; } r; r.o = val; r.n; } )67#endif6869#ifndef reg_page_size70#define reg_page_size 819271#endif7273#ifndef REG_ADDR74#define REG_ADDR( scope, inst, reg ) \75( (inst) + REG_RD_ADDR_##scope##_##reg )76#endif7778#ifndef REG_ADDR_VECT79#define REG_ADDR_VECT( scope, inst, reg, index ) \80( (inst) + REG_RD_ADDR_##scope##_##reg + \81(index) * STRIDE_##scope##_##reg )82#endif8384/* C-code for register scope strmux */8586/* Register rw_cfg, scope strmux, type rw */87typedef struct {88unsigned int dma0 : 3;89unsigned int dma1 : 3;90unsigned int dma2 : 3;91unsigned int dma3 : 3;92unsigned int dma4 : 3;93unsigned int dma5 : 3;94unsigned int dma6 : 3;95unsigned int dma7 : 3;96unsigned int dma8 : 3;97unsigned int dma9 : 3;98unsigned int dummy1 : 2;99} reg_strmux_rw_cfg;100#define REG_RD_ADDR_strmux_rw_cfg 0101#define REG_WR_ADDR_strmux_rw_cfg 0102103104/* Constants */105enum {106regk_strmux_ata = 0x00000003,107regk_strmux_eth0 = 0x00000001,108regk_strmux_eth1 = 0x00000004,109regk_strmux_ext0 = 0x00000001,110regk_strmux_ext1 = 0x00000001,111regk_strmux_ext2 = 0x00000001,112regk_strmux_ext3 = 0x00000001,113regk_strmux_iop0 = 0x00000002,114regk_strmux_iop1 = 0x00000001,115regk_strmux_off = 0x00000000,116regk_strmux_p21 = 0x00000004,117regk_strmux_rw_cfg_default = 0x00000000,118regk_strmux_ser0 = 0x00000002,119regk_strmux_ser1 = 0x00000002,120regk_strmux_ser2 = 0x00000004,121regk_strmux_ser3 = 0x00000003,122regk_strmux_sser0 = 0x00000003,123regk_strmux_sser1 = 0x00000003,124regk_strmux_strcop = 0x00000002125};126#endif /* __strmux_defs_h */127128129