Path: blob/master/arch/cris/include/asm/cacheflush.h
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#ifndef _CRIS_CACHEFLUSH_H1#define _CRIS_CACHEFLUSH_H23/* Keep includes the same across arches. */4#include <linux/mm.h>56/* The cache doesn't need to be flushed when TLB entries change because7* the cache is mapped to physical memory, not virtual memory8*/9#define flush_cache_all() do { } while (0)10#define flush_cache_mm(mm) do { } while (0)11#define flush_cache_dup_mm(mm) do { } while (0)12#define flush_cache_range(vma, start, end) do { } while (0)13#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)14#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 015#define flush_dcache_page(page) do { } while (0)16#define flush_dcache_mmap_lock(mapping) do { } while (0)17#define flush_dcache_mmap_unlock(mapping) do { } while (0)18#define flush_icache_range(start, end) do { } while (0)19#define flush_icache_page(vma,pg) do { } while (0)20#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)21#define flush_cache_vmap(start, end) do { } while (0)22#define flush_cache_vunmap(start, end) do { } while (0)2324#define copy_to_user_page(vma, page, vaddr, dst, src, len) \25memcpy(dst, src, len)26#define copy_from_user_page(vma, page, vaddr, dst, src, len) \27memcpy(dst, src, len)2829int change_page_attr(struct page *page, int numpages, pgprot_t prot);3031#endif /* _CRIS_CACHEFLUSH_H */323334