CoCalc -- head-uc-fr401.S

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/frv/kernel/head-uc-fr401.S
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/* head-uc-fr401.S: FR401/3/5 uc-linux specific bits of initialisation
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 *
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 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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 * Written by David Howells ([email protected])
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License
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 * as published by the Free Software Foundation; either version
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 * 2 of the License, or (at your option) any later version.
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 */
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <asm/ptrace.h>
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#include <asm/page.h>
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#include <asm/spr-regs.h>
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#include <asm/mb86943a.h>
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#include "head.inc"
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#define __400_DBR0	0xfe000e00
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#define __400_DBR1	0xfe000e08
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#define __400_DBR2	0xfe000e10	/* not on FR401 */
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#define __400_DBR3	0xfe000e18	/* not on FR401 */
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#define __400_DAM0	0xfe000f00
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#define __400_DAM1	0xfe000f08
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#define __400_DAM2	0xfe000f10	/* not on FR401 */
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#define __400_DAM3	0xfe000f18	/* not on FR401 */
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#define __400_LGCR	0xfe000010
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#define __400_LCR	0xfe000100
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#define __400_LSBR	0xfe000c00
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	__INIT
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	.balign		4
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###############################################################################
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#
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# describe the position and layout of the SDRAM controller registers
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#
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#	ENTRY:			EXIT:
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# GR5	-			cacheline size
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# GR11	-			displacement of 2nd SDRAM addr reg from GR14
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# GR12	-			displacement of 3rd SDRAM addr reg from GR14
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# GR13	-			displacement of 4th SDRAM addr reg from GR14
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# GR14	-			address of 1st SDRAM addr reg
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# GR15	-			amount to shift address by to match SDRAM addr reg
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# GR26	&__head_reference	[saved]
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# GR30	LED address		[saved]
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# CC0	-			T if DBR0 is present
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# CC1	-			T if DBR1 is present
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# CC2	-			T if DBR2 is present (not FR401/FR401A)
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# CC3	-			T if DBR3 is present (not FR401/FR401A)
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#
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###############################################################################
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	.globl		__head_fr401_describe_sdram
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__head_fr401_describe_sdram:
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	sethi.p		%hi(__400_DBR0),gr14
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	setlo		%lo(__400_DBR0),gr14
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	setlos.p	#__400_DBR1-__400_DBR0,gr11
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	setlos		#__400_DBR2-__400_DBR0,gr12
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	setlos.p	#__400_DBR3-__400_DBR0,gr13
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	setlos		#32,gr5			; cacheline size
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	setlos.p	#0,gr15			; amount to shift addr reg by
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	# specify which DBR regs are present
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	setlos		#0x00ff,gr4
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	movgs		gr4,cccr
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	movsg		psr,gr3			; check for FR401/FR401A
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	srli		gr3,#25,gr3
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	subicc		gr3,#0x20>>1,gr0,icc0
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	bnelr		icc0,#1
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	setlos		#0x000f,gr4
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	movgs		gr4,cccr
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	bralr
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###############################################################################
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#
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# rearrange the bus controller registers
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#
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#	ENTRY:			EXIT:
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# GR26	&__head_reference	[saved]
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# GR30	LED address		revised LED address
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#
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###############################################################################
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	.globl		__head_fr401_set_busctl
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__head_fr401_set_busctl:
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	sethi.p		%hi(__400_LGCR),gr4
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	setlo		%lo(__400_LGCR),gr4
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	sethi.p		%hi(__400_LSBR),gr10
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	setlo		%lo(__400_LSBR),gr10
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	sethi.p		%hi(__400_LCR),gr11
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	setlo		%lo(__400_LCR),gr11
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	# set the bus controller
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	ldi		@(gr4,#0),gr5
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	ori		gr5,#0xff,gr5		; make sure all chip-selects are enabled
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	sti		gr5,@(gr4,#0)
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	sethi.p		%hi(__region_CS1),gr4
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	setlo		%lo(__region_CS1),gr4
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	sethi.p		%hi(__region_CS1_M),gr5
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	setlo		%lo(__region_CS1_M),gr5
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	sethi.p		%hi(__region_CS1_C),gr6
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	setlo		%lo(__region_CS1_C),gr6
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	sti		gr4,@(gr10,#1*0x08)
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	sti		gr5,@(gr10,#1*0x08+0x100)
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	sti		gr6,@(gr11,#1*0x08)
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	sethi.p		%hi(__region_CS2),gr4
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	setlo		%lo(__region_CS2),gr4
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	sethi.p		%hi(__region_CS2_M),gr5
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	setlo		%lo(__region_CS2_M),gr5
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	sethi.p		%hi(__region_CS2_C),gr6
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	setlo		%lo(__region_CS2_C),gr6
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	sti		gr4,@(gr10,#2*0x08)
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	sti		gr5,@(gr10,#2*0x08+0x100)
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	sti		gr6,@(gr11,#2*0x08)
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	sethi.p		%hi(__region_CS3),gr4
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	setlo		%lo(__region_CS3),gr4
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	sethi.p		%hi(__region_CS3_M),gr5
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	setlo		%lo(__region_CS3_M),gr5
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	sethi.p		%hi(__region_CS3_C),gr6
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	setlo		%lo(__region_CS3_C),gr6
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	sti		gr4,@(gr10,#3*0x08)
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	sti		gr5,@(gr10,#3*0x08+0x100)
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	sti		gr6,@(gr11,#3*0x08)
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	sethi.p		%hi(__region_CS4),gr4
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	setlo		%lo(__region_CS4),gr4
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	sethi.p		%hi(__region_CS4_M),gr5
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	setlo		%lo(__region_CS4_M),gr5
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	sethi.p		%hi(__region_CS4_C),gr6
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	setlo		%lo(__region_CS4_C),gr6
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	sti		gr4,@(gr10,#4*0x08)
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	sti		gr5,@(gr10,#4*0x08+0x100)
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	sti		gr6,@(gr11,#4*0x08)
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	sethi.p		%hi(__region_CS5),gr4
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	setlo		%lo(__region_CS5),gr4
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	sethi.p		%hi(__region_CS5_M),gr5
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	setlo		%lo(__region_CS5_M),gr5
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	sethi.p		%hi(__region_CS5_C),gr6
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	setlo		%lo(__region_CS5_C),gr6
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	sti		gr4,@(gr10,#5*0x08)
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	sti		gr5,@(gr10,#5*0x08+0x100)
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	sti		gr6,@(gr11,#5*0x08)
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	sethi.p		%hi(__region_CS6),gr4
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	setlo		%lo(__region_CS6),gr4
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	sethi.p		%hi(__region_CS6_M),gr5
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	setlo		%lo(__region_CS6_M),gr5
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	sethi.p		%hi(__region_CS6_C),gr6
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	setlo		%lo(__region_CS6_C),gr6
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	sti		gr4,@(gr10,#6*0x08)
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	sti		gr5,@(gr10,#6*0x08+0x100)
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	sti		gr6,@(gr11,#6*0x08)
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	sethi.p		%hi(__region_CS7),gr4
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	setlo		%lo(__region_CS7),gr4
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	sethi.p		%hi(__region_CS7_M),gr5
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	setlo		%lo(__region_CS7_M),gr5
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	sethi.p		%hi(__region_CS7_C),gr6
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	setlo		%lo(__region_CS7_C),gr6
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	sti		gr4,@(gr10,#7*0x08)
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	sti		gr5,@(gr10,#7*0x08+0x100)
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	sti		gr6,@(gr11,#7*0x08)
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	membar
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	bar
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	# adjust LED bank address
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	sethi.p		%hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
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	setlo		%lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
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	bralr
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###############################################################################
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#
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# determine the total SDRAM size
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#
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#	ENTRY:			EXIT:
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# GR25	-			SDRAM size
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# GR26	&__head_reference	[saved]
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# GR30	LED address		[saved]
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#
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###############################################################################
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	.globl		__head_fr401_survey_sdram
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__head_fr401_survey_sdram:
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	sethi.p		%hi(__400_DAM0),gr11
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	setlo		%lo(__400_DAM0),gr11
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	sethi.p		%hi(__400_DBR0),gr12
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	setlo		%lo(__400_DBR0),gr12
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	sethi.p		%hi(0xfe000000),gr17		; unused SDRAM DBR value
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	setlo		%lo(0xfe000000),gr17
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	setlos		#0,gr25
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	ldi		@(gr12,#0x00),gr4		; DAR0
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	subcc		gr4,gr17,gr0,icc0
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	beq		icc0,#0,__head_no_DCS0
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	ldi		@(gr11,#0x00),gr6		; DAM0: bits 31:20 match addr 31:20
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	add		gr25,gr6,gr25
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	addi		gr25,#1,gr25
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__head_no_DCS0:
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	ldi		@(gr12,#0x08),gr4		; DAR1
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	subcc		gr4,gr17,gr0,icc0
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	beq		icc0,#0,__head_no_DCS1
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	ldi		@(gr11,#0x08),gr6		; DAM1: bits 31:20 match addr 31:20
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	add		gr25,gr6,gr25
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	addi		gr25,#1,gr25
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__head_no_DCS1:
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	# FR401/FR401A does not have DCS2/3
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	movsg		psr,gr3
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	srli		gr3,#25,gr3
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	subicc		gr3,#0x20>>1,gr0,icc0
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	beq		icc0,#0,__head_no_DCS3
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	ldi		@(gr12,#0x10),gr4		; DAR2
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	subcc		gr4,gr17,gr0,icc0
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	beq		icc0,#0,__head_no_DCS2
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	ldi		@(gr11,#0x10),gr6		; DAM2: bits 31:20 match addr 31:20
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	add		gr25,gr6,gr25
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	addi		gr25,#1,gr25
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__head_no_DCS2:
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	ldi		@(gr12,#0x18),gr4		; DAR3
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	subcc		gr4,gr17,gr0,icc0
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	beq		icc0,#0,__head_no_DCS3
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	ldi		@(gr11,#0x18),gr6		; DAM3: bits 31:20 match addr 31:20
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	add		gr25,gr6,gr25
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	addi		gr25,#1,gr25
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__head_no_DCS3:
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	bralr
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###############################################################################
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#
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# set the protection map with the I/DAMPR registers
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#
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#	ENTRY:			EXIT:
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# GR25	SDRAM size		[saved]
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# GR26	&__head_reference	[saved]
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# GR30	LED address		[saved]
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#
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###############################################################################
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	.globl		__head_fr401_set_protection
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__head_fr401_set_protection:
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	movsg		lr,gr27
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	# set the I/O region protection registers for FR401/3/5
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	sethi.p		%hi(__region_IO),gr5
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	setlo		%lo(__region_IO),gr5
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	ori		gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
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	movgs		gr0,iampr7
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	movgs		gr5,dampr7			; General I/O tile
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	# need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
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	# - start with the highest numbered registers
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	sethi.p		%hi(__kernel_image_end),gr8
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	setlo		%lo(__kernel_image_end),gr8
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	sethi.p		%hi(32768),gr4			; allow for a maximal allocator bitmap
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	setlo		%lo(32768),gr4
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	add		gr8,gr4,gr8
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	sethi.p		%hi(1024*2048-1),gr4		; round up to nearest 2MiB
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	setlo		%lo(1024*2048-1),gr4
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	add.p		gr8,gr4,gr8
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	not		gr4,gr4
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	and		gr8,gr4,gr8
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	sethi.p		%hi(__page_offset),gr9
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	setlo		%lo(__page_offset),gr9
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	add		gr9,gr25,gr9
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	# GR8 = base of uncovered RAM
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	# GR9 = top of uncovered RAM
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#ifdef CONFIG_MB93093_PDK
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	sethi.p		%hi(__region_CS2),gr4
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	setlo		%lo(__region_CS2),gr4
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	ori		gr4,#xAMPRx_SS_1Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr4
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	movgs		gr4,dampr6
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	movgs		gr0,iampr6
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#else
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	call		__head_split_region
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	movgs		gr4,iampr6
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	movgs		gr5,dampr6
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#endif
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	call		__head_split_region
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	movgs		gr4,iampr5
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	movgs		gr5,dampr5
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	call		__head_split_region
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	movgs		gr4,iampr4
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	movgs		gr5,dampr4
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	call		__head_split_region
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	movgs		gr4,iampr3
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	movgs		gr5,dampr3
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	call		__head_split_region
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	movgs		gr4,iampr2
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	movgs		gr5,dampr2
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	call		__head_split_region
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	movgs		gr4,iampr1
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	movgs		gr5,dampr1
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	# cover kernel core image with kernel-only segment
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	sethi.p		%hi(__page_offset),gr8
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	setlo		%lo(__page_offset),gr8
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	call		__head_split_region
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#ifdef CONFIG_PROTECT_KERNEL
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	ori.p		gr4,#xAMPRx_S_KERNEL,gr4
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	ori		gr5,#xAMPRx_S_KERNEL,gr5
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#endif
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	movgs		gr4,iampr0
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	movgs		gr5,dampr0
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	jmpl		@(gr27,gr0)
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