/* head-uc-fr555.S: FR555 uc-linux specific bits of initialisation1*2* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.3* Written by David Howells ([email protected])4*5* This program is free software; you can redistribute it and/or6* modify it under the terms of the GNU General Public License7* as published by the Free Software Foundation; either version8* 2 of the License, or (at your option) any later version.9*/1011#include <linux/init.h>12#include <linux/threads.h>13#include <linux/linkage.h>14#include <asm/ptrace.h>15#include <asm/page.h>16#include <asm/spr-regs.h>17#include <asm/mb86943a.h>18#include "head.inc"192021#define __551_DARS0 0xfeff010022#define __551_DARS1 0xfeff010423#define __551_DARS2 0xfeff010824#define __551_DARS3 0xfeff010c25#define __551_DAMK0 0xfeff011026#define __551_DAMK1 0xfeff011427#define __551_DAMK2 0xfeff011828#define __551_DAMK3 0xfeff011c29#define __551_LCR 0xfeff110030#define __551_LSBR 0xfeff1c003132__INIT33.balign 43435###############################################################################36#37# describe the position and layout of the SDRAM controller registers38#39# ENTRY: EXIT:40# GR5 - cacheline size41# GR11 - displacement of 2nd SDRAM addr reg from GR1442# GR12 - displacement of 3rd SDRAM addr reg from GR1443# GR13 - displacement of 4th SDRAM addr reg from GR1444# GR14 - address of 1st SDRAM addr reg45# GR15 - amount to shift address by to match SDRAM addr reg46# GR26 &__head_reference [saved]47# GR30 LED address [saved]48# CC0 - T if DARS0 is present49# CC1 - T if DARS1 is present50# CC2 - T if DARS2 is present51# CC3 - T if DARS3 is present52#53###############################################################################54.globl __head_fr555_describe_sdram55__head_fr555_describe_sdram:56sethi.p %hi(__551_DARS0),gr1457setlo %lo(__551_DARS0),gr1458setlos.p #__551_DARS1-__551_DARS0,gr1159setlos #__551_DARS2-__551_DARS0,gr1260setlos.p #__551_DARS3-__551_DARS0,gr1361setlos #64,gr5 ; cacheline size62setlos #20,gr15 ; amount to shift addr by63setlos #0x00ff,gr464movgs gr4,cccr ; extant DARS/DAMK regs65bralr6667###############################################################################68#69# rearrange the bus controller registers70#71# ENTRY: EXIT:72# GR26 &__head_reference [saved]73# GR30 LED address revised LED address74#75###############################################################################76.globl __head_fr555_set_busctl77__head_fr555_set_busctl:78LEDS 0x100f79sethi.p %hi(__551_LSBR),gr1080setlo %lo(__551_LSBR),gr1081sethi.p %hi(__551_LCR),gr1182setlo %lo(__551_LCR),gr118384# set the bus controller85sethi.p %hi(__region_CS1),gr486setlo %lo(__region_CS1),gr487sethi.p %hi(__region_CS1_M),gr588setlo %lo(__region_CS1_M),gr589sethi.p %hi(__region_CS1_C),gr690setlo %lo(__region_CS1_C),gr691sti gr4,@(gr10,#1*0x08)92sti gr5,@(gr10,#1*0x08+0x100)93sti gr6,@(gr11,#1*0x08)94sethi.p %hi(__region_CS2),gr495setlo %lo(__region_CS2),gr496sethi.p %hi(__region_CS2_M),gr597setlo %lo(__region_CS2_M),gr598sethi.p %hi(__region_CS2_C),gr699setlo %lo(__region_CS2_C),gr6100sti gr4,@(gr10,#2*0x08)101sti gr5,@(gr10,#2*0x08+0x100)102sti gr6,@(gr11,#2*0x08)103sethi.p %hi(__region_CS3),gr4104setlo %lo(__region_CS3),gr4105sethi.p %hi(__region_CS3_M),gr5106setlo %lo(__region_CS3_M),gr5107sethi.p %hi(__region_CS3_C),gr6108setlo %lo(__region_CS3_C),gr6109sti gr4,@(gr10,#3*0x08)110sti gr5,@(gr10,#3*0x08+0x100)111sti gr6,@(gr11,#3*0x08)112sethi.p %hi(__region_CS4),gr4113setlo %lo(__region_CS4),gr4114sethi.p %hi(__region_CS4_M),gr5115setlo %lo(__region_CS4_M),gr5116sethi.p %hi(__region_CS4_C),gr6117setlo %lo(__region_CS4_C),gr6118sti gr4,@(gr10,#4*0x08)119sti gr5,@(gr10,#4*0x08+0x100)120sti gr6,@(gr11,#4*0x08)121sethi.p %hi(__region_CS5),gr4122setlo %lo(__region_CS5),gr4123sethi.p %hi(__region_CS5_M),gr5124setlo %lo(__region_CS5_M),gr5125sethi.p %hi(__region_CS5_C),gr6126setlo %lo(__region_CS5_C),gr6127sti gr4,@(gr10,#5*0x08)128sti gr5,@(gr10,#5*0x08+0x100)129sti gr6,@(gr11,#5*0x08)130sethi.p %hi(__region_CS6),gr4131setlo %lo(__region_CS6),gr4132sethi.p %hi(__region_CS6_M),gr5133setlo %lo(__region_CS6_M),gr5134sethi.p %hi(__region_CS6_C),gr6135setlo %lo(__region_CS6_C),gr6136sti gr4,@(gr10,#6*0x08)137sti gr5,@(gr10,#6*0x08+0x100)138sti gr6,@(gr11,#6*0x08)139sethi.p %hi(__region_CS7),gr4140setlo %lo(__region_CS7),gr4141sethi.p %hi(__region_CS7_M),gr5142setlo %lo(__region_CS7_M),gr5143sethi.p %hi(__region_CS7_C),gr6144setlo %lo(__region_CS7_C),gr6145sti gr4,@(gr10,#7*0x08)146sti gr5,@(gr10,#7*0x08+0x100)147sti gr6,@(gr11,#7*0x08)148membar149bar150151# adjust LED bank address152#ifdef CONFIG_MB93091_VDK153sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30154setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30155#endif156bralr157158###############################################################################159#160# determine the total SDRAM size161#162# ENTRY: EXIT:163# GR25 - SDRAM size164# GR26 &__head_reference [saved]165# GR30 LED address [saved]166#167###############################################################################168.globl __head_fr555_survey_sdram169__head_fr555_survey_sdram:170sethi.p %hi(__551_DAMK0),gr11171setlo %lo(__551_DAMK0),gr11172sethi.p %hi(__551_DARS0),gr12173setlo %lo(__551_DARS0),gr12174175sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value176setlo %lo(0xfff),gr17177setlos #0,gr25178179ldi @(gr11,#0x00),gr6 ; DAMK0: bits 11:0 match addr 11:0180subcc gr6,gr17,gr0,icc0181beq icc0,#0,__head_no_DCS0182ldi @(gr12,#0x00),gr4 ; DARS0183add gr25,gr6,gr25184addi gr25,#1,gr25185__head_no_DCS0:186187ldi @(gr11,#0x04),gr6 ; DAMK1: bits 11:0 match addr 11:0188subcc gr6,gr17,gr0,icc0189beq icc0,#0,__head_no_DCS1190ldi @(gr12,#0x04),gr4 ; DARS1191add gr25,gr6,gr25192addi gr25,#1,gr25193__head_no_DCS1:194195ldi @(gr11,#0x8),gr6 ; DAMK2: bits 11:0 match addr 11:0196subcc gr6,gr17,gr0,icc0197beq icc0,#0,__head_no_DCS2198ldi @(gr12,#0x8),gr4 ; DARS2199add gr25,gr6,gr25200addi gr25,#1,gr25201__head_no_DCS2:202203ldi @(gr11,#0xc),gr6 ; DAMK3: bits 11:0 match addr 11:0204subcc gr6,gr17,gr0,icc0205beq icc0,#0,__head_no_DCS3206ldi @(gr12,#0xc),gr4 ; DARS3207add gr25,gr6,gr25208addi gr25,#1,gr25209__head_no_DCS3:210211slli gr25,#20,gr25 ; shift [11:0] -> [31:20]212bralr213214###############################################################################215#216# set the protection map with the I/DAMPR registers217#218# ENTRY: EXIT:219# GR25 SDRAM size saved220# GR30 LED address saved221#222###############################################################################223.globl __head_fr555_set_protection224__head_fr555_set_protection:225movsg lr,gr27226227sethi.p %hi(0xfff00000),gr11228setlo %lo(0xfff00000),gr11229230# set the I/O region protection registers for FR555231sethi.p %hi(__region_IO),gr7232setlo %lo(__region_IO),gr7233ori gr7,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5234movgs gr0,iampr15235movgs gr0,iamlr15236movgs gr5,dampr15237movgs gr7,damlr15238239# need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible240# - start with the highest numbered registers241sethi.p %hi(__kernel_image_end),gr8242setlo %lo(__kernel_image_end),gr8243sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap244setlo %lo(32768),gr4245add gr8,gr4,gr8246sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB247setlo %lo(1024*2048-1),gr4248add.p gr8,gr4,gr8249not gr4,gr4250and gr8,gr4,gr8251252sethi.p %hi(__page_offset),gr9253setlo %lo(__page_offset),gr9254add gr9,gr25,gr9255256# GR8 = base of uncovered RAM257# GR9 = top of uncovered RAM258# GR11 - mask for DAMLR/IAMLR regs259#260call __head_split_region261movgs gr4,iampr14262movgs gr6,iamlr14263movgs gr5,dampr14264movgs gr7,damlr14265call __head_split_region266movgs gr4,iampr13267movgs gr6,iamlr13268movgs gr5,dampr13269movgs gr7,damlr13270call __head_split_region271movgs gr4,iampr12272movgs gr6,iamlr12273movgs gr5,dampr12274movgs gr7,damlr12275call __head_split_region276movgs gr4,iampr11277movgs gr6,iamlr11278movgs gr5,dampr11279movgs gr7,damlr11280call __head_split_region281movgs gr4,iampr10282movgs gr6,iamlr10283movgs gr5,dampr10284movgs gr7,damlr10285call __head_split_region286movgs gr4,iampr9287movgs gr6,iamlr9288movgs gr5,dampr9289movgs gr7,damlr9290call __head_split_region291movgs gr4,iampr8292movgs gr6,iamlr8293movgs gr5,dampr8294movgs gr7,damlr8295296call __head_split_region297movgs gr4,iampr7298movgs gr6,iamlr7299movgs gr5,dampr7300movgs gr7,damlr7301call __head_split_region302movgs gr4,iampr6303movgs gr6,iamlr6304movgs gr5,dampr6305movgs gr7,damlr6306call __head_split_region307movgs gr4,iampr5308movgs gr6,iamlr5309movgs gr5,dampr5310movgs gr7,damlr5311call __head_split_region312movgs gr4,iampr4313movgs gr6,iamlr4314movgs gr5,dampr4315movgs gr7,damlr4316call __head_split_region317movgs gr4,iampr3318movgs gr6,iamlr3319movgs gr5,dampr3320movgs gr7,damlr3321call __head_split_region322movgs gr4,iampr2323movgs gr6,iamlr2324movgs gr5,dampr2325movgs gr7,damlr2326call __head_split_region327movgs gr4,iampr1328movgs gr6,iamlr1329movgs gr5,dampr1330movgs gr7,damlr1331332# cover kernel core image with kernel-only segment333sethi.p %hi(__page_offset),gr8334setlo %lo(__page_offset),gr8335call __head_split_region336337#ifdef CONFIG_PROTECT_KERNEL338ori.p gr4,#xAMPRx_S_KERNEL,gr4339ori gr5,#xAMPRx_S_KERNEL,gr5340#endif341342movgs gr4,iampr0343movgs gr6,iamlr0344movgs gr5,dampr0345movgs gr7,damlr0346jmpl @(gr27,gr0)347348349