CoCalc -- gcc_intrin.h

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/ia64/include/asm/gcc_intrin.h
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#ifndef _ASM_IA64_GCC_INTRIN_H
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#define _ASM_IA64_GCC_INTRIN_H
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/*
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 *
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 * Copyright (C) 2002,2003 Jun Nakajima <[email protected]>
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 * Copyright (C) 2002,2003 Suresh Siddha <[email protected]>
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 */
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#include <linux/types.h>
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#include <linux/compiler.h>
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/* define this macro to get some asm stmts included in 'c' files */
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#define ASM_SUPPORTED
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/* Optimization barrier */
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/* The "volatile" is due to gcc bugs */
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#define ia64_barrier()	asm volatile ("":::"memory")
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#define ia64_stop()	asm volatile (";;"::)
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#define ia64_invala_gr(regnum)	asm volatile ("invala.e r%0" :: "i"(regnum))
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#define ia64_invala_fr(regnum)	asm volatile ("invala.e f%0" :: "i"(regnum))
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#define ia64_flushrs() asm volatile ("flushrs;;":::"memory")
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#define ia64_loadrs() asm volatile ("loadrs;;":::"memory")
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extern void ia64_bad_param_for_setreg (void);
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extern void ia64_bad_param_for_getreg (void);
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#ifdef __KERNEL__
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register unsigned long ia64_r13 asm ("r13") __used;
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#endif
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#define ia64_native_setreg(regnum, val)						\
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({										\
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	switch (regnum) {							\
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	    case _IA64_REG_PSR_L:						\
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		    asm volatile ("mov psr.l=%0" :: "r"(val) : "memory");	\
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		    break;							\
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	    case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC:				\
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		    asm volatile ("mov ar%0=%1" ::				\
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		    			  "i" (regnum - _IA64_REG_AR_KR0),	\
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					  "r"(val): "memory");			\
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		    break;							\
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	    case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1:			\
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		    asm volatile ("mov cr%0=%1" ::				\
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				          "i" (regnum - _IA64_REG_CR_DCR),	\
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					  "r"(val): "memory" );			\
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		    break;							\
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	    case _IA64_REG_SP:							\
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		    asm volatile ("mov r12=%0" ::				\
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			    		  "r"(val): "memory");			\
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		    break;							\
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	    case _IA64_REG_GP:							\
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		    asm volatile ("mov gp=%0" :: "r"(val) : "memory");		\
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		break;								\
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	    default:								\
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		    ia64_bad_param_for_setreg();				\
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		    break;							\
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	}									\
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})
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#define ia64_native_getreg(regnum)						\
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({										\
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	__u64 ia64_intri_res;							\
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										\
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	switch (regnum) {							\
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	case _IA64_REG_GP:							\
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		asm volatile ("mov %0=gp" : "=r"(ia64_intri_res));		\
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		break;								\
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	case _IA64_REG_IP:							\
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		asm volatile ("mov %0=ip" : "=r"(ia64_intri_res));		\
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		break;								\
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	case _IA64_REG_PSR:							\
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		asm volatile ("mov %0=psr" : "=r"(ia64_intri_res));		\
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		break;								\
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	case _IA64_REG_TP:	/* for current() */				\
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		ia64_intri_res = ia64_r13;					\
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		break;								\
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	case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC:				\
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		asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res)		\
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				      : "i"(regnum - _IA64_REG_AR_KR0));	\
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		break;								\
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	case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1:				\
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		asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res)		\
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				      : "i" (regnum - _IA64_REG_CR_DCR));	\
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		break;								\
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	case _IA64_REG_SP:							\
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		asm volatile ("mov %0=sp" : "=r" (ia64_intri_res));		\
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		break;								\
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	default:								\
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		ia64_bad_param_for_getreg();					\
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		break;								\
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	}									\
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	ia64_intri_res;								\
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})
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#define ia64_hint_pause 0
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#define ia64_hint(mode)						\
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({								\
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	switch (mode) {						\
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	case ia64_hint_pause:					\
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		asm volatile ("hint @pause" ::: "memory");	\
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		break;						\
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	}							\
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})
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/* Integer values for mux1 instruction */
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#define ia64_mux1_brcst 0
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#define ia64_mux1_mix   8
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#define ia64_mux1_shuf  9
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#define ia64_mux1_alt  10
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#define ia64_mux1_rev  11
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#define ia64_mux1(x, mode)							\
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({										\
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	__u64 ia64_intri_res;							\
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										\
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	switch (mode) {								\
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	case ia64_mux1_brcst:							\
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		asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x));	\
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		break;								\
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	case ia64_mux1_mix:							\
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		asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x));	\
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		break;								\
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	case ia64_mux1_shuf:							\
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		asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x));	\
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		break;								\
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	case ia64_mux1_alt:							\
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		asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x));	\
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		break;								\
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	case ia64_mux1_rev:							\
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		asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x));	\
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		break;								\
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	}									\
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	ia64_intri_res;								\
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})
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#if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
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# define ia64_popcnt(x)		__builtin_popcountl(x)
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#else
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# define ia64_popcnt(x)						\
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  ({								\
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	__u64 ia64_intri_res;					\
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	asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x));	\
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								\
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	ia64_intri_res;						\
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  })
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#endif
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#define ia64_getf_exp(x)					\
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({								\
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	long ia64_intri_res;					\
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								\
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	asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x));	\
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								\
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	ia64_intri_res;						\
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})
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#define ia64_shrp(a, b, count)								\
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({											\
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	__u64 ia64_intri_res;								\
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	asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count));	\
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	ia64_intri_res;									\
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})
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#define ia64_ldfs(regnum, x)					\
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({								\
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	register double __f__ asm ("f"#regnum);			\
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	asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x));	\
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})
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#define ia64_ldfd(regnum, x)					\
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({								\
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	register double __f__ asm ("f"#regnum);			\
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	asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x));	\
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})
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#define ia64_ldfe(regnum, x)					\
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({								\
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	register double __f__ asm ("f"#regnum);			\
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	asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x));	\
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})
188

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#define ia64_ldf8(regnum, x)					\
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({								\
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	register double __f__ asm ("f"#regnum);			\
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	asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x));	\
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})
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#define ia64_ldf_fill(regnum, x)				\
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({								\
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	register double __f__ asm ("f"#regnum);			\
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	asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x));	\
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})
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201
#define ia64_st4_rel_nta(m, val)					\
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({									\
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	asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val));	\
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})
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#define ia64_stfs(x, regnum)						\
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({									\
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	register double __f__ asm ("f"#regnum);				\
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	asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory");	\
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})
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#define ia64_stfd(x, regnum)						\
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({									\
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	register double __f__ asm ("f"#regnum);				\
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	asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory");	\
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})
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#define ia64_stfe(x, regnum)						\
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({									\
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	register double __f__ asm ("f"#regnum);				\
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	asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory");	\
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})
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#define ia64_stf8(x, regnum)						\
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({									\
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	register double __f__ asm ("f"#regnum);				\
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	asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory");	\
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})
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#define ia64_stf_spill(x, regnum)						\
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({										\
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	register double __f__ asm ("f"#regnum);					\
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	asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory");	\
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})
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236
#define ia64_fetchadd4_acq(p, inc)						\
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({										\
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										\
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	__u64 ia64_intri_res;							\
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	asm volatile ("fetchadd4.acq %0=[%1],%2"				\
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				: "=r"(ia64_intri_res) : "r"(p), "i" (inc)	\
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				: "memory");					\
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										\
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	ia64_intri_res;								\
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})
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#define ia64_fetchadd4_rel(p, inc)						\
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({										\
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	__u64 ia64_intri_res;							\
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	asm volatile ("fetchadd4.rel %0=[%1],%2"				\
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				: "=r"(ia64_intri_res) : "r"(p), "i" (inc)	\
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				: "memory");					\
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										\
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	ia64_intri_res;								\
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})
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#define ia64_fetchadd8_acq(p, inc)						\
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({										\
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										\
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	__u64 ia64_intri_res;							\
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	asm volatile ("fetchadd8.acq %0=[%1],%2"				\
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				: "=r"(ia64_intri_res) : "r"(p), "i" (inc)	\
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				: "memory");					\
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										\
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	ia64_intri_res;								\
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})
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268
#define ia64_fetchadd8_rel(p, inc)						\
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({										\
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	__u64 ia64_intri_res;							\
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	asm volatile ("fetchadd8.rel %0=[%1],%2"				\
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				: "=r"(ia64_intri_res) : "r"(p), "i" (inc)	\
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				: "memory");					\
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										\
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	ia64_intri_res;								\
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})
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278
#define ia64_xchg1(ptr,x)							\
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({										\
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	__u64 ia64_intri_res;							\
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	asm volatile ("xchg1 %0=[%1],%2"					\
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		      : "=r" (ia64_intri_res) : "r" (ptr), "r" (x) : "memory");	\
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	ia64_intri_res;								\
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})
285

286
#define ia64_xchg2(ptr,x)						\
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({									\
288
	__u64 ia64_intri_res;						\
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	asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res)	\
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		      : "r" (ptr), "r" (x) : "memory");			\
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	ia64_intri_res;							\
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})
293

294
#define ia64_xchg4(ptr,x)						\
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({									\
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	__u64 ia64_intri_res;						\
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	asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res)	\
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		      : "r" (ptr), "r" (x) : "memory");			\
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	ia64_intri_res;							\
300
})
301

302
#define ia64_xchg8(ptr,x)						\
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({									\
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	__u64 ia64_intri_res;						\
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	asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res)	\
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		      : "r" (ptr), "r" (x) : "memory");			\
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	ia64_intri_res;							\
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})
309

310
#define ia64_cmpxchg1_acq(ptr, new, old)						\
311
({											\
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	__u64 ia64_intri_res;								\
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	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
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	asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv":					\
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			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
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	ia64_intri_res;									\
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})
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319
#define ia64_cmpxchg1_rel(ptr, new, old)						\
320
({											\
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	__u64 ia64_intri_res;								\
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	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
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	asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv":					\
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			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
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	ia64_intri_res;									\
326
})
327

328
#define ia64_cmpxchg2_acq(ptr, new, old)						\
329
({											\
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	__u64 ia64_intri_res;								\
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	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
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	asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv":					\
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			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
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	ia64_intri_res;									\
335
})
336

337
#define ia64_cmpxchg2_rel(ptr, new, old)						\
338
({											\
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	__u64 ia64_intri_res;								\
340
	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
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											\
342
	asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv":					\
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			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
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	ia64_intri_res;									\
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})
346

347
#define ia64_cmpxchg4_acq(ptr, new, old)						\
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({											\
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	__u64 ia64_intri_res;								\
350
	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
351
	asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv":					\
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			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
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	ia64_intri_res;									\
354
})
355

356
#define ia64_cmpxchg4_rel(ptr, new, old)						\
357
({											\
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	__u64 ia64_intri_res;								\
359
	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
360
	asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv":					\
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			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
362
	ia64_intri_res;									\
363
})
364

365
#define ia64_cmpxchg8_acq(ptr, new, old)						\
366
({											\
367
	__u64 ia64_intri_res;								\
368
	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
369
	asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv":					\
370
			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
371
	ia64_intri_res;									\
372
})
373

374
#define ia64_cmpxchg8_rel(ptr, new, old)						\
375
({											\
376
	__u64 ia64_intri_res;								\
377
	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
378
											\
379
	asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv":					\
380
			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
381
	ia64_intri_res;									\
382
})
383

384
#define ia64_mf()	asm volatile ("mf" ::: "memory")
385
#define ia64_mfa()	asm volatile ("mf.a" ::: "memory")
386

387
#define ia64_invala() asm volatile ("invala" ::: "memory")
388

389
#define ia64_native_thash(addr)							\
390
({										\
391
	unsigned long ia64_intri_res;						\
392
	asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr));	\
393
	ia64_intri_res;								\
394
})
395

396
#define ia64_srlz_i()	asm volatile (";; srlz.i ;;" ::: "memory")
397
#define ia64_srlz_d()	asm volatile (";; srlz.d" ::: "memory");
398

399
#ifdef HAVE_SERIALIZE_DIRECTIVE
400
# define ia64_dv_serialize_data()		asm volatile (".serialize.data");
401
# define ia64_dv_serialize_instruction()	asm volatile (".serialize.instruction");
402
#else
403
# define ia64_dv_serialize_data()
404
# define ia64_dv_serialize_instruction()
405
#endif
406

407
#define ia64_nop(x)	asm volatile ("nop %0"::"i"(x));
408

409
#define ia64_itci(addr)	asm volatile ("itc.i %0;;" :: "r"(addr) : "memory")
410

411
#define ia64_itcd(addr)	asm volatile ("itc.d %0;;" :: "r"(addr) : "memory")
412

413

414
#define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1"				\
415
					     :: "r"(trnum), "r"(addr) : "memory")
416

417
#define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1"				\
418
					     :: "r"(trnum), "r"(addr) : "memory")
419

420
#define ia64_tpa(addr)								\
421
({										\
422
	unsigned long ia64_pa;							\
423
	asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory");	\
424
	ia64_pa;								\
425
})
426

427
#define __ia64_set_dbr(index, val)						\
428
	asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
429

430
#define ia64_set_ibr(index, val)						\
431
	asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
432

433
#define ia64_set_pkr(index, val)						\
434
	asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
435

436
#define ia64_set_pmc(index, val)						\
437
	asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
438

439
#define ia64_set_pmd(index, val)						\
440
	asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
441

442
#define ia64_native_set_rr(index, val)							\
443
	asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory");
444

445
#define ia64_native_get_cpuid(index)							\
446
({											\
447
	unsigned long ia64_intri_res;							\
448
	asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index));	\
449
	ia64_intri_res;									\
450
})
451

452
#define __ia64_get_dbr(index)							\
453
({										\
454
	unsigned long ia64_intri_res;						\
455
	asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index));	\
456
	ia64_intri_res;								\
457
})
458

459
#define ia64_get_ibr(index)							\
460
({										\
461
	unsigned long ia64_intri_res;						\
462
	asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index));	\
463
	ia64_intri_res;								\
464
})
465

466
#define ia64_get_pkr(index)							\
467
({										\
468
	unsigned long ia64_intri_res;						\
469
	asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index));	\
470
	ia64_intri_res;								\
471
})
472

473
#define ia64_get_pmc(index)							\
474
({										\
475
	unsigned long ia64_intri_res;						\
476
	asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index));	\
477
	ia64_intri_res;								\
478
})
479

480

481
#define ia64_native_get_pmd(index)						\
482
({										\
483
	unsigned long ia64_intri_res;						\
484
	asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index));	\
485
	ia64_intri_res;								\
486
})
487

488
#define ia64_native_get_rr(index)						\
489
({										\
490
	unsigned long ia64_intri_res;						\
491
	asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index));	\
492
	ia64_intri_res;								\
493
})
494

495
#define ia64_native_fc(addr)	asm volatile ("fc %0" :: "r"(addr) : "memory")
496

497

498
#define ia64_sync_i()	asm volatile (";; sync.i" ::: "memory")
499

500
#define ia64_native_ssm(mask)	asm volatile ("ssm %0":: "i"((mask)) : "memory")
501
#define ia64_native_rsm(mask)	asm volatile ("rsm %0":: "i"((mask)) : "memory")
502
#define ia64_sum(mask)	asm volatile ("sum %0":: "i"((mask)) : "memory")
503
#define ia64_rum(mask)	asm volatile ("rum %0":: "i"((mask)) : "memory")
504

505
#define ia64_ptce(addr)	asm volatile ("ptc.e %0" :: "r"(addr))
506

507
#define ia64_native_ptcga(addr, size)						\
508
do {										\
509
	asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory");	\
510
	ia64_dv_serialize_data();						\
511
} while (0)
512

513
#define ia64_ptcl(addr, size)							\
514
do {										\
515
	asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory");	\
516
	ia64_dv_serialize_data();						\
517
} while (0)
518

519
#define ia64_ptri(addr, size)						\
520
	asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory")
521

522
#define ia64_ptrd(addr, size)						\
523
	asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory")
524

525
#define ia64_ttag(addr)							\
526
({									  \
527
	__u64 ia64_intri_res;						   \
528
	asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr));   \
529
	ia64_intri_res;							 \
530
})
531

532

533
/* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */
534

535
#define ia64_lfhint_none   0
536
#define ia64_lfhint_nt1    1
537
#define ia64_lfhint_nt2    2
538
#define ia64_lfhint_nta    3
539

540
#define ia64_lfetch(lfhint, y)					\
541
({								\
542
        switch (lfhint) {					\
543
        case ia64_lfhint_none:					\
544
                asm volatile ("lfetch [%0]" : : "r"(y));	\
545
                break;						\
546
        case ia64_lfhint_nt1:					\
547
                asm volatile ("lfetch.nt1 [%0]" : : "r"(y));	\
548
                break;						\
549
        case ia64_lfhint_nt2:					\
550
                asm volatile ("lfetch.nt2 [%0]" : : "r"(y));	\
551
                break;						\
552
        case ia64_lfhint_nta:					\
553
                asm volatile ("lfetch.nta [%0]" : : "r"(y));	\
554
                break;						\
555
        }							\
556
})
557

558
#define ia64_lfetch_excl(lfhint, y)					\
559
({									\
560
        switch (lfhint) {						\
561
        case ia64_lfhint_none:						\
562
                asm volatile ("lfetch.excl [%0]" :: "r"(y));		\
563
                break;							\
564
        case ia64_lfhint_nt1:						\
565
                asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y));	\
566
                break;							\
567
        case ia64_lfhint_nt2:						\
568
                asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y));	\
569
                break;							\
570
        case ia64_lfhint_nta:						\
571
                asm volatile ("lfetch.excl.nta [%0]" :: "r"(y));	\
572
                break;							\
573
        }								\
574
})
575

576
#define ia64_lfetch_fault(lfhint, y)					\
577
({									\
578
        switch (lfhint) {						\
579
        case ia64_lfhint_none:						\
580
                asm volatile ("lfetch.fault [%0]" : : "r"(y));		\
581
                break;							\
582
        case ia64_lfhint_nt1:						\
583
                asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y));	\
584
                break;							\
585
        case ia64_lfhint_nt2:						\
586
                asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y));	\
587
                break;							\
588
        case ia64_lfhint_nta:						\
589
                asm volatile ("lfetch.fault.nta [%0]" : : "r"(y));	\
590
                break;							\
591
        }								\
592
})
593

594
#define ia64_lfetch_fault_excl(lfhint, y)				\
595
({									\
596
        switch (lfhint) {						\
597
        case ia64_lfhint_none:						\
598
                asm volatile ("lfetch.fault.excl [%0]" :: "r"(y));	\
599
                break;							\
600
        case ia64_lfhint_nt1:						\
601
                asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y));	\
602
                break;							\
603
        case ia64_lfhint_nt2:						\
604
                asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y));	\
605
                break;							\
606
        case ia64_lfhint_nta:						\
607
                asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y));	\
608
                break;							\
609
        }								\
610
})
611

612
#define ia64_native_intrin_local_irq_restore(x)			\
613
do {								\
614
	asm volatile (";;   cmp.ne p6,p7=%0,r0;;"		\
615
		      "(p6) ssm psr.i;"				\
616
		      "(p7) rsm psr.i;;"			\
617
		      "(p6) srlz.d"				\
618
		      :: "r"((x)) : "p6", "p7", "memory");	\
619
} while (0)
620

621
#endif /* _ASM_IA64_GCC_INTRIN_H */
622

623
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