Path: blob/master/arch/ia64/include/asm/intel_intrin.h
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#ifndef _ASM_IA64_INTEL_INTRIN_H1#define _ASM_IA64_INTEL_INTRIN_H2/*3* Intel Compiler Intrinsics4*5* Copyright (C) 2002,2003 Jun Nakajima <[email protected]>6* Copyright (C) 2002,2003 Suresh Siddha <[email protected]>7* Copyright (C) 2005,2006 Hongjiu Lu <[email protected]>8*9*/10#include <ia64intrin.h>1112#define ia64_barrier() __memory_barrier()1314#define ia64_stop() /* Nothing: As of now stop bit is generated for each15* intrinsic16*/1718#define ia64_native_getreg __getReg19#define ia64_native_setreg __setReg2021#define ia64_hint __hint22#define ia64_hint_pause __hint_pause2324#define ia64_mux1_brcst _m64_mux1_brcst25#define ia64_mux1_mix _m64_mux1_mix26#define ia64_mux1_shuf _m64_mux1_shuf27#define ia64_mux1_alt _m64_mux1_alt28#define ia64_mux1_rev _m64_mux1_rev2930#define ia64_mux1(x,v) _m_to_int64(_m64_mux1(_m_from_int64(x), (v)))31#define ia64_popcnt _m64_popcnt32#define ia64_getf_exp __getf_exp33#define ia64_shrp _m64_shrp3435#define ia64_tpa __tpa36#define ia64_invala __invala37#define ia64_invala_gr __invala_gr38#define ia64_invala_fr __invala_fr39#define ia64_nop __nop40#define ia64_sum __sum41#define ia64_native_ssm __ssm42#define ia64_rum __rum43#define ia64_native_rsm __rsm44#define ia64_native_fc __fc4546#define ia64_ldfs __ldfs47#define ia64_ldfd __ldfd48#define ia64_ldfe __ldfe49#define ia64_ldf8 __ldf850#define ia64_ldf_fill __ldf_fill5152#define ia64_stfs __stfs53#define ia64_stfd __stfd54#define ia64_stfe __stfe55#define ia64_stf8 __stf856#define ia64_stf_spill __stf_spill5758#define ia64_mf __mf59#define ia64_mfa __mfa6061#define ia64_fetchadd4_acq __fetchadd4_acq62#define ia64_fetchadd4_rel __fetchadd4_rel63#define ia64_fetchadd8_acq __fetchadd8_acq64#define ia64_fetchadd8_rel __fetchadd8_rel6566#define ia64_xchg1 _InterlockedExchange867#define ia64_xchg2 _InterlockedExchange1668#define ia64_xchg4 _InterlockedExchange69#define ia64_xchg8 _InterlockedExchange647071#define ia64_cmpxchg1_rel _InterlockedCompareExchange8_rel72#define ia64_cmpxchg1_acq _InterlockedCompareExchange8_acq73#define ia64_cmpxchg2_rel _InterlockedCompareExchange16_rel74#define ia64_cmpxchg2_acq _InterlockedCompareExchange16_acq75#define ia64_cmpxchg4_rel _InterlockedCompareExchange_rel76#define ia64_cmpxchg4_acq _InterlockedCompareExchange_acq77#define ia64_cmpxchg8_rel _InterlockedCompareExchange64_rel78#define ia64_cmpxchg8_acq _InterlockedCompareExchange64_acq7980#define __ia64_set_dbr(index, val) \81__setIndReg(_IA64_REG_INDR_DBR, index, val)82#define ia64_set_ibr(index, val) \83__setIndReg(_IA64_REG_INDR_IBR, index, val)84#define ia64_set_pkr(index, val) \85__setIndReg(_IA64_REG_INDR_PKR, index, val)86#define ia64_set_pmc(index, val) \87__setIndReg(_IA64_REG_INDR_PMC, index, val)88#define ia64_set_pmd(index, val) \89__setIndReg(_IA64_REG_INDR_PMD, index, val)90#define ia64_native_set_rr(index, val) \91__setIndReg(_IA64_REG_INDR_RR, index, val)9293#define ia64_native_get_cpuid(index) \94__getIndReg(_IA64_REG_INDR_CPUID, index)95#define __ia64_get_dbr(index) __getIndReg(_IA64_REG_INDR_DBR, index)96#define ia64_get_ibr(index) __getIndReg(_IA64_REG_INDR_IBR, index)97#define ia64_get_pkr(index) __getIndReg(_IA64_REG_INDR_PKR, index)98#define ia64_get_pmc(index) __getIndReg(_IA64_REG_INDR_PMC, index)99#define ia64_native_get_pmd(index) __getIndReg(_IA64_REG_INDR_PMD, index)100#define ia64_native_get_rr(index) __getIndReg(_IA64_REG_INDR_RR, index)101102#define ia64_srlz_d __dsrlz103#define ia64_srlz_i __isrlz104105#define ia64_dv_serialize_data()106#define ia64_dv_serialize_instruction()107108#define ia64_st1_rel __st1_rel109#define ia64_st2_rel __st2_rel110#define ia64_st4_rel __st4_rel111#define ia64_st8_rel __st8_rel112113/* FIXME: need st4.rel.nta intrinsic */114#define ia64_st4_rel_nta __st4_rel115116#define ia64_ld1_acq __ld1_acq117#define ia64_ld2_acq __ld2_acq118#define ia64_ld4_acq __ld4_acq119#define ia64_ld8_acq __ld8_acq120121#define ia64_sync_i __synci122#define ia64_native_thash __thash123#define ia64_native_ttag __ttag124#define ia64_itcd __itcd125#define ia64_itci __itci126#define ia64_itrd __itrd127#define ia64_itri __itri128#define ia64_ptce __ptce129#define ia64_ptcl __ptcl130#define ia64_native_ptcg __ptcg131#define ia64_native_ptcga __ptcga132#define ia64_ptri __ptri133#define ia64_ptrd __ptrd134#define ia64_dep_mi _m64_dep_mi135136/* Values for lfhint in __lfetch and __lfetch_fault */137138#define ia64_lfhint_none __lfhint_none139#define ia64_lfhint_nt1 __lfhint_nt1140#define ia64_lfhint_nt2 __lfhint_nt2141#define ia64_lfhint_nta __lfhint_nta142143#define ia64_lfetch __lfetch144#define ia64_lfetch_excl __lfetch_excl145#define ia64_lfetch_fault __lfetch_fault146#define ia64_lfetch_fault_excl __lfetch_fault_excl147148#define ia64_native_intrin_local_irq_restore(x) \149do { \150if ((x) != 0) { \151ia64_native_ssm(IA64_PSR_I); \152ia64_srlz_d(); \153} else { \154ia64_native_rsm(IA64_PSR_I); \155} \156} while (0)157158#define __builtin_trap() __break(0);159160#endif /* _ASM_IA64_INTEL_INTRIN_H */161162163