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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/ia64/kernel/cyclone.c
10817 views
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#include <linux/module.h>

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#include <linux/smp.h>

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#include <linux/time.h>

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#include <linux/errno.h>

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#include <linux/timex.h>

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#include <linux/clocksource.h>

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#include <asm/io.h>

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/* IBM Summit (EXA) Cyclone counter code*/

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#define CYCLONE_CBAR_ADDR 0xFEB00CD0

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#define CYCLONE_PMCC_OFFSET 0x51A0

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#define CYCLONE_MPMC_OFFSET 0x51D0

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#define CYCLONE_MPCS_OFFSET 0x51A8

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#define CYCLONE_TIMER_FREQ 100000000

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int use_cyclone;

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void __init cyclone_setup(void)

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{

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	use_cyclone = 1;

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}

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static void __iomem *cyclone_mc;

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static cycle_t read_cyclone(struct clocksource *cs)

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{

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	return (cycle_t)readq((void __iomem *)cyclone_mc);

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}

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static struct clocksource clocksource_cyclone = {

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        .name           = "cyclone",

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        .rating         = 300,

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        .read           = read_cyclone,

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        .mask           = (1LL << 40) - 1,

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        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,

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};

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int __init init_cyclone_clock(void)

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{

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	u64 __iomem *reg;

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	u64 base;	/* saved cyclone base address */

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	u64 offset;	/* offset from pageaddr to cyclone_timer register */

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	int i;

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	u32 __iomem *cyclone_timer;	/* Cyclone MPMC0 register */

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	if (!use_cyclone)

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		return 0;

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	printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");

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	/* find base address */

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	offset = (CYCLONE_CBAR_ADDR);

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	reg = ioremap_nocache(offset, sizeof(u64));

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	if(!reg){

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		printk(KERN_ERR "Summit chipset: Could not find valid CBAR"

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				" register.\n");

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		use_cyclone = 0;

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		return -ENODEV;

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	}

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	base = readq(reg);

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	iounmap(reg);

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	if(!base){

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		printk(KERN_ERR "Summit chipset: Could not find valid CBAR"

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				" value.\n");

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		use_cyclone = 0;

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		return -ENODEV;

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	}

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	/* setup PMCC */

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	offset = (base + CYCLONE_PMCC_OFFSET);

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	reg = ioremap_nocache(offset, sizeof(u64));

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	if(!reg){

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		printk(KERN_ERR "Summit chipset: Could not find valid PMCC"

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				" register.\n");

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		use_cyclone = 0;

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		return -ENODEV;

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	}

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	writel(0x00000001,reg);

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	iounmap(reg);

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	/* setup MPCS */

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	offset = (base + CYCLONE_MPCS_OFFSET);

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	reg = ioremap_nocache(offset, sizeof(u64));

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	if(!reg){

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		printk(KERN_ERR "Summit chipset: Could not find valid MPCS"

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				" register.\n");

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		use_cyclone = 0;

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		return -ENODEV;

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	}

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	writel(0x00000001,reg);

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	iounmap(reg);

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	/* map in cyclone_timer */

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	offset = (base + CYCLONE_MPMC_OFFSET);

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	cyclone_timer = ioremap_nocache(offset, sizeof(u32));

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	if(!cyclone_timer){

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		printk(KERN_ERR "Summit chipset: Could not find valid MPMC"

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				" register.\n");

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		use_cyclone = 0;

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		return -ENODEV;

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	}

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	/*quick test to make sure its ticking*/

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	for(i=0; i<3; i++){

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		u32 old = readl(cyclone_timer);

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		int stall = 100;

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		while(stall--) barrier();

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		if(readl(cyclone_timer) == old){

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			printk(KERN_ERR "Summit chipset: Counter not counting!"

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					" DISABLED\n");

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			iounmap(cyclone_timer);

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			cyclone_timer = NULL;

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			use_cyclone = 0;

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			return -ENODEV;

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		}

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	}

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	/* initialize last tick */

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	cyclone_mc = cyclone_timer;

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	clocksource_cyclone.fsys_mmio = cyclone_timer;

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	clocksource_register_hz(&clocksource_cyclone, CYCLONE_TIMER_FREQ);

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	return 0;

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}

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__initcall(init_cyclone_clock);

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