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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
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/* 

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 * This file is subject to the terms and conditions of the GNU General Public

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 * License.  See the file "COPYING" in the main directory of this archive

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 * for more details.

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 *

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 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.

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 */

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#include <asm/types.h>

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#include <asm/sn/shub_mmr.h>

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#define DEADLOCKBIT	SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT

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#define WRITECOUNTMASK	SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK

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#define ALIAS_OFFSET	8

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	.global	sn2_ptc_deadlock_recovery_core

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	.proc  	sn2_ptc_deadlock_recovery_core

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sn2_ptc_deadlock_recovery_core:

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	.regstk 6,0,0,0

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	ptc0  	 = in0

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	data0 	 = in1

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	ptc1  	 = in2

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	data1 	 = in3

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	piowc 	 = in4

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	zeroval  = in5

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	piowcphy = r30

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	psrsave  = r2

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	scr1	 = r16

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	scr2	 = r17

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	mask	 = r18

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	extr.u	piowcphy=piowc,0,61;;	// Convert piowc to uncached physical address

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	dep	piowcphy=-1,piowcphy,63,1

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	movl	mask=WRITECOUNTMASK

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	mov	r8=r0

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1:

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	cmp.ne  p8,p9=r0,ptc1		// Test for shub type (ptc1 non-null on shub1)

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					// p8 = 1 if shub1, p9 = 1 if shub2

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	add	scr2=ALIAS_OFFSET,piowc	// Address of WRITE_STATUS alias register 

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	mov	scr1=7;;		// Clear DEADLOCK, WRITE_ERROR, MULTI_WRITE_ERROR

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(p8)	st8.rel	[scr2]=scr1;;

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(p9)	ld8.acq	scr1=[scr2];;

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5:	ld8.acq	scr1=[piowc];;		// Wait for PIOs to complete.

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	hint	@pause

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	and	scr2=scr1,mask;;	// mask of writecount bits

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	cmp.ne	p6,p0=zeroval,scr2

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(p6)	br.cond.sptk 5b

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	////////////// BEGIN PHYSICAL MODE ////////////////////

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	mov psrsave=psr			// Disable IC (no PMIs)

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	rsm psr.i | psr.dt | psr.ic;;

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	srlz.i;;

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	st8.rel [ptc0]=data0		// Write PTC0 & wait for completion.

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5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.

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	hint	@pause

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	and	scr2=scr1,mask;;	// mask of writecount bits

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	cmp.ne	p6,p0=zeroval,scr2

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(p6)	br.cond.sptk 5b;;

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	tbit.nz	p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK

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(p7)	cmp.ne p7,p0=r0,ptc1;;		// Test for non-null ptc1

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(p7)	st8.rel [ptc1]=data1;;		// Now write PTC1.

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5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.

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	hint	@pause

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	and	scr2=scr1,mask;;	// mask of writecount bits

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	cmp.ne	p6,p0=zeroval,scr2

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(p6)	br.cond.sptk 5b

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	tbit.nz	p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK

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	mov psr.l=psrsave;;		// Reenable IC

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	srlz.i;;

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	////////////// END   PHYSICAL MODE ////////////////////

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(p8)	add	r8=1,r8

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(p8)	br.cond.spnt 1b;;		// Repeat if DEADLOCK occurred.

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	br.ret.sptk	rp

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	.endp sn2_ptc_deadlock_recovery_core

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