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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/m32r/include/asm/m32700ut/m32700ut_pld.h
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#ifndef _M32700UT_M32700UT_PLD_H

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#define _M32700UT_M32700UT_PLD_H

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/*

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 * include/asm-m32r/m32700ut/m32700ut_pld.h

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 *

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 * Definitions for Programmable Logic Device(PLD) on M32700UT board.

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 *

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 * Copyright (c) 2002	Takeo Takahashi

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 *

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 * This file is subject to the terms and conditions of the GNU General

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 * Public License.  See the file "COPYING" in the main directory of

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 * this archive for more details.

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 */

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#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV)

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#define PLD_PLAT_BASE		0x04c00000

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#else

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#error "no platform configuration"

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#endif

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#ifndef __ASSEMBLY__

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/*

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 * C functions use non-cache address.

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 */

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#define PLD_BASE		(PLD_PLAT_BASE /* + NONCACHE_OFFSET */)

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#define __reg8			(volatile unsigned char *)

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#define __reg16			(volatile unsigned short *)

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#define __reg32			(volatile unsigned int *)

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#else

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#define PLD_BASE		(PLD_PLAT_BASE + NONCACHE_OFFSET)

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#define __reg8

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#define __reg16

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#define __reg32

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#endif /* __ASSEMBLY__ */

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/* CFC */

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#define	PLD_CFRSTCR		__reg16(PLD_BASE + 0x0000)

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#define PLD_CFSTS		__reg16(PLD_BASE + 0x0002)

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#define PLD_CFIMASK		__reg16(PLD_BASE + 0x0004)

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#define PLD_CFBUFCR		__reg16(PLD_BASE + 0x0006)

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#define PLD_CFVENCR		__reg16(PLD_BASE + 0x0008)

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#define PLD_CFCR0		__reg16(PLD_BASE + 0x000a)

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#define PLD_CFCR1		__reg16(PLD_BASE + 0x000c)

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#define PLD_IDERSTCR		__reg16(PLD_BASE + 0x0010)

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/* MMC */

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#define PLD_MMCCR		__reg16(PLD_BASE + 0x4000)

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#define PLD_MMCMOD		__reg16(PLD_BASE + 0x4002)

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#define PLD_MMCSTS		__reg16(PLD_BASE + 0x4006)

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#define PLD_MMCBAUR		__reg16(PLD_BASE + 0x400a)

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#define PLD_MMCCMDBCUT		__reg16(PLD_BASE + 0x400c)

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#define PLD_MMCCDTBCUT		__reg16(PLD_BASE + 0x400e)

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#define PLD_MMCDET		__reg16(PLD_BASE + 0x4010)

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#define PLD_MMCWP		__reg16(PLD_BASE + 0x4012)

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#define PLD_MMCWDATA		__reg16(PLD_BASE + 0x5000)

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#define PLD_MMCRDATA		__reg16(PLD_BASE + 0x6000)

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#define PLD_MMCCMDDATA		__reg16(PLD_BASE + 0x7000)

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#define PLD_MMCRSPDATA		__reg16(PLD_BASE + 0x7006)

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/* ICU

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 *  ICUISTS:	status register

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 *  ICUIREQ0: 	request register

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 *  ICUIREQ1: 	request register

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 *  ICUCR3:	control register for CFIREQ# interrupt

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 *  ICUCR4:	control register for CFC Card insert interrupt

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 *  ICUCR5:	control register for CFC Card eject interrupt

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 *  ICUCR6:	control register for external interrupt

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 *  ICUCR11:	control register for MMC Card insert/eject interrupt

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 *  ICUCR13:	control register for SC error interrupt

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 *  ICUCR14:	control register for SC receive interrupt

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 *  ICUCR15:	control register for SC send interrupt

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 *  ICUCR16:	control register for SIO0 receive interrupt

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 *  ICUCR17:	control register for SIO0 send interrupt

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 */

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#if !defined(CONFIG_PLAT_USRV)

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#define PLD_IRQ_INT0		(M32700UT_PLD_IRQ_BASE + 0)	/* None */

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#define PLD_IRQ_INT1		(M32700UT_PLD_IRQ_BASE + 1)	/* reserved */

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#define PLD_IRQ_INT2		(M32700UT_PLD_IRQ_BASE + 2)	/* reserved */

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#define PLD_IRQ_CFIREQ		(M32700UT_PLD_IRQ_BASE + 3)	/* CF IREQ */

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#define PLD_IRQ_CFC_INSERT	(M32700UT_PLD_IRQ_BASE + 4)	/* CF Insert */

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#define PLD_IRQ_CFC_EJECT	(M32700UT_PLD_IRQ_BASE + 5)	/* CF Eject */

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#define PLD_IRQ_EXINT		(M32700UT_PLD_IRQ_BASE + 6)	/* EXINT */

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#define PLD_IRQ_INT7		(M32700UT_PLD_IRQ_BASE + 7)	/* reserved */

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#define PLD_IRQ_INT8		(M32700UT_PLD_IRQ_BASE + 8)	/* reserved */

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#define PLD_IRQ_INT9		(M32700UT_PLD_IRQ_BASE + 9)	/* reserved */

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#define PLD_IRQ_INT10		(M32700UT_PLD_IRQ_BASE + 10)	/* reserved */

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#define PLD_IRQ_MMCCARD		(M32700UT_PLD_IRQ_BASE + 11)	/* MMC Insert/Eject */

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#define PLD_IRQ_INT12		(M32700UT_PLD_IRQ_BASE + 12)	/* reserved */

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#define PLD_IRQ_SC_ERROR	(M32700UT_PLD_IRQ_BASE + 13)	/* SC error */

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#define PLD_IRQ_SC_RCV		(M32700UT_PLD_IRQ_BASE + 14)	/* SC receive */

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#define PLD_IRQ_SC_SND		(M32700UT_PLD_IRQ_BASE + 15)	/* SC send */

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#define PLD_IRQ_SIO0_RCV	(M32700UT_PLD_IRQ_BASE + 16)	/* SIO receive */

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#define PLD_IRQ_SIO0_SND	(M32700UT_PLD_IRQ_BASE + 17)	/* SIO send */

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#define PLD_IRQ_INT18		(M32700UT_PLD_IRQ_BASE + 18)	/* reserved */

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#define PLD_IRQ_INT19		(M32700UT_PLD_IRQ_BASE + 19)	/* reserved */

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#define PLD_IRQ_INT20		(M32700UT_PLD_IRQ_BASE + 20)	/* reserved */

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#define PLD_IRQ_INT21		(M32700UT_PLD_IRQ_BASE + 21)	/* reserved */

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#define PLD_IRQ_INT22		(M32700UT_PLD_IRQ_BASE + 22)	/* reserved */

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#define PLD_IRQ_INT23		(M32700UT_PLD_IRQ_BASE + 23)	/* reserved */

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#define PLD_IRQ_INT24		(M32700UT_PLD_IRQ_BASE + 24)	/* reserved */

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#define PLD_IRQ_INT25		(M32700UT_PLD_IRQ_BASE + 25)	/* reserved */

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#define PLD_IRQ_INT26		(M32700UT_PLD_IRQ_BASE + 26)	/* reserved */

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#define PLD_IRQ_INT27		(M32700UT_PLD_IRQ_BASE + 27)	/* reserved */

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#define PLD_IRQ_INT28		(M32700UT_PLD_IRQ_BASE + 28)	/* reserved */

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#define PLD_IRQ_INT29		(M32700UT_PLD_IRQ_BASE + 29)	/* reserved */

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#define PLD_IRQ_INT30		(M32700UT_PLD_IRQ_BASE + 30)	/* reserved */

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#define PLD_IRQ_INT31		(M32700UT_PLD_IRQ_BASE + 31)	/* reserved */

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#else	/* CONFIG_PLAT_USRV */

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#define PLD_IRQ_INT0		(M32700UT_PLD_IRQ_BASE + 0)	/* None */

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#define PLD_IRQ_INT1		(M32700UT_PLD_IRQ_BASE + 1)	/* reserved */

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#define PLD_IRQ_INT2		(M32700UT_PLD_IRQ_BASE + 2)	/* reserved */

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#define PLD_IRQ_CF0		(M32700UT_PLD_IRQ_BASE + 3)	/* CF0# */

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#define PLD_IRQ_CF1		(M32700UT_PLD_IRQ_BASE + 4)	/* CF1# */

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#define PLD_IRQ_CF2		(M32700UT_PLD_IRQ_BASE + 5)	/* CF2# */

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#define PLD_IRQ_CF3		(M32700UT_PLD_IRQ_BASE + 6)	/* CF3# */

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#define PLD_IRQ_CF4		(M32700UT_PLD_IRQ_BASE + 7)	/* CF4# */

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#define PLD_IRQ_INT8		(M32700UT_PLD_IRQ_BASE + 8)	/* reserved */

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#define PLD_IRQ_INT9		(M32700UT_PLD_IRQ_BASE + 9)	/* reserved */

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#define PLD_IRQ_INT10		(M32700UT_PLD_IRQ_BASE + 10)	/* reserved */

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#define PLD_IRQ_INT11		(M32700UT_PLD_IRQ_BASE + 11)	/* reserved */

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#define PLD_IRQ_UART0		(M32700UT_PLD_IRQ_BASE + 12)	/* UARTIRQ0 */

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#define PLD_IRQ_UART1		(M32700UT_PLD_IRQ_BASE + 13)	/* UARTIRQ1 */

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#define PLD_IRQ_INT14		(M32700UT_PLD_IRQ_BASE + 14)	/* reserved */

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#define PLD_IRQ_INT15		(M32700UT_PLD_IRQ_BASE + 15)	/* reserved */

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#define PLD_IRQ_SNDINT		(M32700UT_PLD_IRQ_BASE + 16)	/* SNDINT# */

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#define PLD_IRQ_INT17		(M32700UT_PLD_IRQ_BASE + 17)	/* reserved */

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#define PLD_IRQ_INT18		(M32700UT_PLD_IRQ_BASE + 18)	/* reserved */

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#define PLD_IRQ_INT19		(M32700UT_PLD_IRQ_BASE + 19)	/* reserved */

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#define PLD_IRQ_INT20		(M32700UT_PLD_IRQ_BASE + 20)	/* reserved */

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#define PLD_IRQ_INT21		(M32700UT_PLD_IRQ_BASE + 21)	/* reserved */

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#define PLD_IRQ_INT22		(M32700UT_PLD_IRQ_BASE + 22)	/* reserved */

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#define PLD_IRQ_INT23		(M32700UT_PLD_IRQ_BASE + 23)	/* reserved */

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#define PLD_IRQ_INT24		(M32700UT_PLD_IRQ_BASE + 24)	/* reserved */

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#define PLD_IRQ_INT25		(M32700UT_PLD_IRQ_BASE + 25)	/* reserved */

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#define PLD_IRQ_INT26		(M32700UT_PLD_IRQ_BASE + 26)	/* reserved */

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#define PLD_IRQ_INT27		(M32700UT_PLD_IRQ_BASE + 27)	/* reserved */

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#define PLD_IRQ_INT28		(M32700UT_PLD_IRQ_BASE + 28)	/* reserved */

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#define PLD_IRQ_INT29		(M32700UT_PLD_IRQ_BASE + 29)	/* reserved */

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#define PLD_IRQ_INT30		(M32700UT_PLD_IRQ_BASE + 30)	/* reserved */

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#endif	/* CONFIG_PLAT_USRV */

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#define PLD_ICUISTS		__reg16(PLD_BASE + 0x8002)

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#define PLD_ICUISTS_VECB_MASK	(0xf000)

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#define PLD_ICUISTS_VECB(x)	((x) & PLD_ICUISTS_VECB_MASK)

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#define PLD_ICUISTS_ISN_MASK	(0x07c0)

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#define PLD_ICUISTS_ISN(x)	((x) & PLD_ICUISTS_ISN_MASK)

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#define PLD_ICUIREQ0		__reg16(PLD_BASE + 0x8004)

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#define PLD_ICUIREQ1		__reg16(PLD_BASE + 0x8006)

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#define PLD_ICUCR1		__reg16(PLD_BASE + 0x8100)

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#define PLD_ICUCR2		__reg16(PLD_BASE + 0x8102)

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#define PLD_ICUCR3		__reg16(PLD_BASE + 0x8104)

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#define PLD_ICUCR4		__reg16(PLD_BASE + 0x8106)

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#define PLD_ICUCR5		__reg16(PLD_BASE + 0x8108)

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#define PLD_ICUCR6		__reg16(PLD_BASE + 0x810a)

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#define PLD_ICUCR7		__reg16(PLD_BASE + 0x810c)

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#define PLD_ICUCR8		__reg16(PLD_BASE + 0x810e)

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#define PLD_ICUCR9		__reg16(PLD_BASE + 0x8110)

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#define PLD_ICUCR10		__reg16(PLD_BASE + 0x8112)

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#define PLD_ICUCR11		__reg16(PLD_BASE + 0x8114)

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#define PLD_ICUCR12		__reg16(PLD_BASE + 0x8116)

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#define PLD_ICUCR13		__reg16(PLD_BASE + 0x8118)

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#define PLD_ICUCR14		__reg16(PLD_BASE + 0x811a)

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#define PLD_ICUCR15		__reg16(PLD_BASE + 0x811c)

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#define PLD_ICUCR16		__reg16(PLD_BASE + 0x811e)

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#define PLD_ICUCR17		__reg16(PLD_BASE + 0x8120)

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#define PLD_ICUCR_IEN		(0x1000)

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#define PLD_ICUCR_IREQ		(0x0100)

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#define PLD_ICUCR_ISMOD00	(0x0000)	/* Low edge */

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#define PLD_ICUCR_ISMOD01	(0x0010)	/* Low level */

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#define PLD_ICUCR_ISMOD02	(0x0020)	/* High edge */

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#define PLD_ICUCR_ISMOD03	(0x0030)	/* High level */

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#define PLD_ICUCR_ILEVEL0	(0x0000)

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#define PLD_ICUCR_ILEVEL1	(0x0001)

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#define PLD_ICUCR_ILEVEL2	(0x0002)

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#define PLD_ICUCR_ILEVEL3	(0x0003)

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#define PLD_ICUCR_ILEVEL4	(0x0004)

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#define PLD_ICUCR_ILEVEL5	(0x0005)

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#define PLD_ICUCR_ILEVEL6	(0x0006)

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#define PLD_ICUCR_ILEVEL7	(0x0007)

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/* Power Control of MMC and CF */

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#define PLD_CPCR		__reg16(PLD_BASE + 0x14000)

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#define PLD_CPCR_CF		0x0001

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#define PLD_CPCR_MMC		0x0002

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/* LED Control

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 *

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 * 1: DIP swich side

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 * 2: Reset switch side

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 */

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#define PLD_IOLEDCR		__reg16(PLD_BASE + 0x14002)

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#define PLD_IOLED_1_ON		0x001

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#define PLD_IOLED_1_OFF		0x000

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#define PLD_IOLED_2_ON		0x002

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#define PLD_IOLED_2_OFF		0x000

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/* DIP Switch

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 *  0: Write-protect of Flash Memory (0:protected, 1:non-protected)

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 *  1: -

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 *  2: -

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 *  3: -

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 */

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#define PLD_IOSWSTS		__reg16(PLD_BASE + 0x14004)

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#define	PLD_IOSWSTS_IOSW2	0x0200

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#define	PLD_IOSWSTS_IOSW1	0x0100

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#define	PLD_IOSWSTS_IOWP0	0x0001

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/* CRC */

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#define PLD_CRC7DATA		__reg16(PLD_BASE + 0x18000)

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#define PLD_CRC7INDATA		__reg16(PLD_BASE + 0x18002)

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#define PLD_CRC16DATA		__reg16(PLD_BASE + 0x18004)

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#define PLD_CRC16INDATA		__reg16(PLD_BASE + 0x18006)

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#define PLD_CRC16ADATA		__reg16(PLD_BASE + 0x18008)

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#define PLD_CRC16AINDATA	__reg16(PLD_BASE + 0x1800a)

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/* RTC */

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#define PLD_RTCCR		__reg16(PLD_BASE + 0x1c000)

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#define PLD_RTCBAUR		__reg16(PLD_BASE + 0x1c002)

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#define PLD_RTCWRDATA		__reg16(PLD_BASE + 0x1c004)

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#define PLD_RTCRDDATA		__reg16(PLD_BASE + 0x1c006)

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#define PLD_RTCRSTODT		__reg16(PLD_BASE + 0x1c008)

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/* SIO0 */

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#define PLD_ESIO0CR		__reg16(PLD_BASE + 0x20000)

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#define	PLD_ESIO0CR_TXEN	0x0001

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#define	PLD_ESIO0CR_RXEN	0x0002

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#define PLD_ESIO0MOD0		__reg16(PLD_BASE + 0x20002)

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#define	PLD_ESIO0MOD0_CTSS	0x0040

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#define	PLD_ESIO0MOD0_RTSS	0x0080

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#define PLD_ESIO0MOD1		__reg16(PLD_BASE + 0x20004)

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#define	PLD_ESIO0MOD1_LMFS	0x0010

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#define PLD_ESIO0STS		__reg16(PLD_BASE + 0x20006)

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#define	PLD_ESIO0STS_TEMP	0x0001

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#define	PLD_ESIO0STS_TXCP	0x0002

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#define	PLD_ESIO0STS_RXCP	0x0004

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#define	PLD_ESIO0STS_TXSC	0x0100

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#define	PLD_ESIO0STS_RXSC	0x0200

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#define PLD_ESIO0STS_TXREADY	(PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)

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#define PLD_ESIO0INTCR		__reg16(PLD_BASE + 0x20008)

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#define	PLD_ESIO0INTCR_TXIEN	0x0002

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#define	PLD_ESIO0INTCR_RXCEN	0x0004

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#define PLD_ESIO0BAUR		__reg16(PLD_BASE + 0x2000a)

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#define PLD_ESIO0TXB		__reg16(PLD_BASE + 0x2000c)

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#define PLD_ESIO0RXB		__reg16(PLD_BASE + 0x2000e)

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/* SIM Card */

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#define PLD_SCCR		__reg16(PLD_BASE + 0x38000)

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#define PLD_SCMOD		__reg16(PLD_BASE + 0x38004)

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#define PLD_SCSTS		__reg16(PLD_BASE + 0x38006)

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#define PLD_SCINTCR		__reg16(PLD_BASE + 0x38008)

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#define PLD_SCBAUR		__reg16(PLD_BASE + 0x3800a)

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#define PLD_SCTXB		__reg16(PLD_BASE + 0x3800c)

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#define PLD_SCRXB		__reg16(PLD_BASE + 0x3800e)

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#endif /* _M32700UT_M32700UT_PLD.H */

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