Path: blob/master/arch/m68k/include/asm/cacheflush_mm.h
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#ifndef _M68K_CACHEFLUSH_H1#define _M68K_CACHEFLUSH_H23#include <linux/mm.h>45/* cache code */6#define FLUSH_I_AND_D (0x00000808)7#define FLUSH_I (0x00000008)89/*10* Cache handling functions11*/1213static inline void flush_icache(void)14{15if (CPU_IS_040_OR_060)16asm volatile ( "nop\n"17" .chip 68040\n"18" cpusha %bc\n"19" .chip 68k");20else {21unsigned long tmp;22asm volatile ( "movec %%cacr,%0\n"23" or.w %1,%0\n"24" movec %0,%%cacr"25: "=&d" (tmp)26: "id" (FLUSH_I));27}28}2930/*31* invalidate the cache for the specified memory range.32* It starts at the physical address specified for33* the given number of bytes.34*/35extern void cache_clear(unsigned long paddr, int len);36/*37* push any dirty cache in the specified memory range.38* It starts at the physical address specified for39* the given number of bytes.40*/41extern void cache_push(unsigned long paddr, int len);4243/*44* push and invalidate pages in the specified user virtual45* memory range.46*/47extern void cache_push_v(unsigned long vaddr, int len);4849/* This is needed whenever the virtual mapping of the current50process changes. */51#define __flush_cache_all() \52({ \53if (CPU_IS_040_OR_060) \54__asm__ __volatile__("nop\n\t" \55".chip 68040\n\t" \56"cpusha %dc\n\t" \57".chip 68k"); \58else { \59unsigned long _tmp; \60__asm__ __volatile__("movec %%cacr,%0\n\t" \61"orw %1,%0\n\t" \62"movec %0,%%cacr" \63: "=&d" (_tmp) \64: "di" (FLUSH_I_AND_D)); \65} \66})6768#define __flush_cache_030() \69({ \70if (CPU_IS_020_OR_030) { \71unsigned long _tmp; \72__asm__ __volatile__("movec %%cacr,%0\n\t" \73"orw %1,%0\n\t" \74"movec %0,%%cacr" \75: "=&d" (_tmp) \76: "di" (FLUSH_I_AND_D)); \77} \78})7980#define flush_cache_all() __flush_cache_all()8182#define flush_cache_vmap(start, end) flush_cache_all()83#define flush_cache_vunmap(start, end) flush_cache_all()8485static inline void flush_cache_mm(struct mm_struct *mm)86{87if (mm == current->mm)88__flush_cache_030();89}9091#define flush_cache_dup_mm(mm) flush_cache_mm(mm)9293/* flush_cache_range/flush_cache_page must be macros to avoid94a dependency on linux/mm.h, which includes this file... */95static inline void flush_cache_range(struct vm_area_struct *vma,96unsigned long start,97unsigned long end)98{99if (vma->vm_mm == current->mm)100__flush_cache_030();101}102103static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)104{105if (vma->vm_mm == current->mm)106__flush_cache_030();107}108109110/* Push the page at kernel virtual address and clear the icache */111/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */112static inline void __flush_page_to_ram(void *vaddr)113{114if (CPU_IS_040_OR_060) {115__asm__ __volatile__("nop\n\t"116".chip 68040\n\t"117"cpushp %%bc,(%0)\n\t"118".chip 68k"119: : "a" (__pa(vaddr)));120} else {121unsigned long _tmp;122__asm__ __volatile__("movec %%cacr,%0\n\t"123"orw %1,%0\n\t"124"movec %0,%%cacr"125: "=&d" (_tmp)126: "di" (FLUSH_I));127}128}129130#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1131#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))132#define flush_dcache_mmap_lock(mapping) do { } while (0)133#define flush_dcache_mmap_unlock(mapping) do { } while (0)134#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))135136extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,137unsigned long addr, int len);138extern void flush_icache_range(unsigned long address, unsigned long endaddr);139140static inline void copy_to_user_page(struct vm_area_struct *vma,141struct page *page, unsigned long vaddr,142void *dst, void *src, int len)143{144flush_cache_page(vma, vaddr, page_to_pfn(page));145memcpy(dst, src, len);146flush_icache_user_range(vma, page, vaddr, len);147}148static inline void copy_from_user_page(struct vm_area_struct *vma,149struct page *page, unsigned long vaddr,150void *dst, void *src, int len)151{152flush_cache_page(vma, vaddr, page_to_pfn(page));153memcpy(dst, src, len);154}155156#endif /* _M68K_CACHEFLUSH_H */157158159