CoCalc -- head-ram.S

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/m68k/platform/68360/head-ram.S
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/* arch/m68knommu/platform/68360/head-ram.S
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 *
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 * Startup code for Motorola 68360
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 *
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 * Copyright 2001 (C) SED Systems, a Division of Calian Ltd.
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 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
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 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
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 *           uClinux Kernel
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 * Copyright (C) Michael Leslie <[email protected]>
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 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
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 * Copyright (C) 1998  D. Jeff Dionne <[email protected]>,
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 *
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 */
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#define ASSEMBLY
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.global _stext
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.global _start
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.global _rambase
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.global _ramvec
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.global _ramstart
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.global _ramend
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.global _quicc_base
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.global _periph_base
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#define	RAMEND                      (CONFIG_RAMBASE + CONFIG_RAMSIZE)
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#define	ROMEND                      (CONFIG_ROMBASE + CONFIG_ROMSIZE)
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#define REGB                        0x1000
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#define PEPAR                       (_dprbase + REGB + 0x0016)
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#define GMR                         (_dprbase + REGB + 0x0040)
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#define OR0                         (_dprbase + REGB + 0x0054)
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#define BR0                         (_dprbase + REGB + 0x0050)
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#define OR1                         (_dprbase + REGB + 0x0064)
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#define BR1                         (_dprbase + REGB + 0x0060)
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#define OR4                         (_dprbase + REGB + 0x0094)
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#define BR4                         (_dprbase + REGB + 0x0090)
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#define OR6                         (_dprbase + REGB + 0x00b4)
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#define BR6                         (_dprbase + REGB + 0x00b0)
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#define OR7                         (_dprbase + REGB + 0x00c4)
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#define BR7                         (_dprbase + REGB + 0x00c0)
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#define MCR                         (_dprbase + REGB + 0x0000)
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#define AVR                         (_dprbase + REGB + 0x0008)
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#define SYPCR                       (_dprbase + REGB + 0x0022)
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#define PLLCR                       (_dprbase + REGB + 0x0010)
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#define CLKOCR                      (_dprbase + REGB + 0x000C)
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#define CDVCR                       (_dprbase + REGB + 0x0014)
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#define BKAR                        (_dprbase + REGB + 0x0030)
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#define BKCR                        (_dprbase + REGB + 0x0034)
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#define SWIV                        (_dprbase + REGB + 0x0023)
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#define PICR                        (_dprbase + REGB + 0x0026)
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#define PITR                        (_dprbase + REGB + 0x002A)
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/* Define for all memory configuration */
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#define MCU_SIM_GMR                 0x00000000
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#define SIM_OR_MASK                 0x0fffffff
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/* Defines for chip select zero - the flash */
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#define SIM_OR0_MASK                0x20000002
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#define SIM_BR0_MASK                0x00000001
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/* Defines for chip select one - the RAM */
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#define SIM_OR1_MASK                0x10000000
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#define SIM_BR1_MASK                0x00000001
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#define MCU_SIM_MBAR_ADRS           0x0003ff00
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#define MCU_SIM_MBAR_BA_MASK        0xfffff000
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#define MCU_SIM_MBAR_AS_MASK        0x00000001
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#define MCU_SIM_PEPAR               0x00B4
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#define MCU_DISABLE_INTRPTS         0x2700
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#define MCU_SIM_AVR                 0x00
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#define MCU_SIM_MCR                 0x00005cff
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#define MCU_SIM_CLKOCR              0x00
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#define MCU_SIM_PLLCR               0x8000
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#define MCU_SIM_CDVCR               0x0000
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#define MCU_SIM_SYPCR               0x0000
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#define MCU_SIM_SWIV                0x00
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#define MCU_SIM_PICR                0x0000
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#define MCU_SIM_PITR                0x0000
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#include <asm/m68360_regs.h>
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/*
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 * By the time this RAM specific code begins to execute, DPRAM
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 * and DRAM should already be mapped and accessible.
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 */
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	.text
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_start:
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_stext:
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	nop
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	ori.w	#MCU_DISABLE_INTRPTS, %sr	/* disable interrupts: */
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	/* We should not need to setup the boot stack the reset should do it. */
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	movea.l	#RAMEND, %sp			/*set up stack at the end of DRAM:*/
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set_mbar_register:
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	moveq.l	#0x07, %d1			/* Setup MBAR */
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	movec	%d1, %dfc
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	lea.l	MCU_SIM_MBAR_ADRS, %a0
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	move.l	#_dprbase, %d0
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	andi.l	#MCU_SIM_MBAR_BA_MASK, %d0
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	ori.l	#MCU_SIM_MBAR_AS_MASK, %d0
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	moves.l	%d0, %a0@
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	moveq.l	#0x05, %d1
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	movec.l	%d1, %dfc
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	/* Now we can begin to access registers in DPRAM */
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set_sim_mcr:
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	/* Set Module Configuration Register */
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	move.l	#MCU_SIM_MCR, MCR
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	/* to do:	Determine cause of reset */
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	/*
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	 *       configure system clock MC68360 p. 6-40
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	 *       (value +1)*osc/128 = system clock
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	 */
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set_sim_clock:
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	move.w	#MCU_SIM_PLLCR, PLLCR
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	move.b	#MCU_SIM_CLKOCR, CLKOCR
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	move.w	#MCU_SIM_CDVCR, CDVCR
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	/* Wait for the PLL to settle */
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	move.w	#16384, %d0
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pll_settle_wait:
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	subi.w	#1, %d0
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	bne	pll_settle_wait
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	/* Setup the system protection register, and watchdog timer register */
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	move.b	#MCU_SIM_SWIV, SWIV
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	move.w	#MCU_SIM_PICR, PICR
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	move.w	#MCU_SIM_PITR, PITR
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	move.w	#MCU_SIM_SYPCR, SYPCR
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	/* Clear DPRAM - system + parameter */
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	movea.l	#_dprbase, %a0
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	movea.l	#_dprbase+0x2000, %a1
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	/* Copy 0 to %a0 until %a0 == %a1 */
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clear_dpram:
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	movel	#0, %a0@+
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	cmpal	%a0, %a1
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	bhi	clear_dpram
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configure_memory_controller:    
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	/* Set up Global Memory Register (GMR) */
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	move.l	#MCU_SIM_GMR, %d0
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	move.l	%d0, GMR
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configure_chip_select_0:
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	move.l	#RAMEND, %d0
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	subi.l	#__ramstart, %d0
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	subq.l	#0x01, %d0
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	eori.l	#SIM_OR_MASK, %d0
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	ori.l	#SIM_OR0_MASK, %d0
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	move.l	%d0, OR0
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	move.l	#__ramstart, %d0
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	ori.l	#SIM_BR0_MASK, %d0
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	move.l	%d0, BR0
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configure_chip_select_1:
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	move.l	#ROMEND, %d0
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	subi.l	#__rom_start, %d0
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	subq.l	#0x01, %d0
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	eori.l	#SIM_OR_MASK, %d0
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	ori.l	#SIM_OR1_MASK, %d0
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	move.l	%d0, OR1
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	move.l	#__rom_start, %d0
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	ori.l	#SIM_BR1_MASK, %d0
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	move.l	%d0, BR1
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	move.w	#MCU_SIM_PEPAR, PEPAR 
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	/* point to vector table: */
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	move.l	#_romvec, %a0
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	move.l	#_ramvec, %a1
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copy_vectors:
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	move.l	%a0@, %d0
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	move.l	%d0, %a1@
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	move.l	%a0@, %a1@
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	addq.l	#0x04, %a0
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	addq.l	#0x04, %a1
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	cmp.l	#_start, %a0
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	blt	copy_vectors
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	move.l	#_ramvec, %a1
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	movec	%a1, %vbr
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	/* Copy data segment from ROM to RAM */
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	moveal	#_stext, %a0
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	moveal	#_sdata, %a1
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	moveal	#_edata, %a2
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	/* Copy %a0 to %a1 until %a1 == %a2 */
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LD1:
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	move.l	%a0@, %d0
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	addq.l	#0x04, %a0
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	move.l	%d0, %a1@
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	addq.l	#0x04, %a1
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	cmp.l	#_edata, %a1
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	blt     LD1
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	moveal	#_sbss, %a0
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	moveal	#_ebss, %a1
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	/* Copy 0 to %a0 until %a0 == %a1 */
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L1:
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	movel	#0, %a0@+
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	cmpal	%a0, %a1
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	bhi	L1
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load_quicc:
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	move.l	#_dprbase, _quicc_base
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store_ram_size:
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	/* Set ram size information */
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	move.l	#_sdata, _rambase
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	move.l	#_ebss, _ramstart
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	move.l	#RAMEND, %d0
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	sub.l	#0x1000, %d0			/* Reserve 4K for stack space.*/
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	move.l	%d0, _ramend			/* Different from RAMEND.*/
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	pea	0
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	pea	env
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	pea	%sp@(4)
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	pea	0
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	lea	init_thread_union, %a2
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	lea	0x2000(%a2), %sp
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lp:
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	jsr	start_kernel
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_exit:
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	jmp	_exit
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	.data
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	.align 4
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env:
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	.long	0
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_quicc_base:
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	.long	0
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_periph_base:
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	.long	0
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_ramvec:
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	.long   0
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_rambase:
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	.long   0
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_ramstart:
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	.long   0
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_ramend:
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	.long   0
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_dprbase:
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	.long	0xffffe000
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	.text
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    /*
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     * These are the exception vectors at boot up, they are copied into RAM
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     * and then overwritten as needed.
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     */
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.section ".data..initvect","awx"
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    .long   RAMEND	/* Reset: Initial Stack Pointer                 - 0.  */
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    .long   _start      /* Reset: Initial Program Counter               - 1.  */
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    .long   buserr      /* Bus Error                                    - 2.  */
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    .long   trap        /* Address Error                                - 3.  */
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    .long   trap        /* Illegal Instruction                          - 4.  */
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    .long   trap        /* Divide by zero                               - 5.  */
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    .long   trap        /* CHK, CHK2 Instructions                       - 6.  */
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    .long   trap        /* TRAPcc, TRAPV Instructions                   - 7.  */
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    .long   trap        /* Privilege Violation                          - 8.  */
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    .long   trap        /* Trace                                        - 9.  */
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    .long   trap        /* Line 1010 Emulator                           - 10. */
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    .long   trap        /* Line 1111 Emualtor                           - 11. */
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    .long   trap        /* Harware Breakpoint                           - 12. */
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    .long   trap        /* (Reserved for Coprocessor Protocol Violation)- 13. */
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    .long   trap        /* Format Error                                 - 14. */
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    .long   trap        /* Uninitialized Interrupt                      - 15. */
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    .long   trap        /* (Unassigned, Reserver)                       - 16. */
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    .long   trap        /* (Unassigned, Reserver)                       - 17. */
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    .long   trap        /* (Unassigned, Reserver)                       - 18. */
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    .long   trap        /* (Unassigned, Reserver)                       - 19. */
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    .long   trap        /* (Unassigned, Reserver)                       - 20. */
305
    .long   trap        /* (Unassigned, Reserver)                       - 21. */
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    .long   trap        /* (Unassigned, Reserver)                       - 22. */
307
    .long   trap        /* (Unassigned, Reserver)                       - 23. */
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    .long   trap        /* Spurious Interrupt                           - 24. */
309
    .long   trap        /* Level 1 Interrupt Autovector                 - 25. */
310
    .long   trap        /* Level 2 Interrupt Autovector                 - 26. */
311
    .long   trap        /* Level 3 Interrupt Autovector                 - 27. */
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    .long   trap        /* Level 4 Interrupt Autovector                 - 28. */
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    .long   trap        /* Level 5 Interrupt Autovector                 - 29. */
314
    .long   trap        /* Level 6 Interrupt Autovector                 - 30. */
315
    .long   trap        /* Level 7 Interrupt Autovector                 - 31. */
316
    .long   system_call /* Trap Instruction Vectors 0                   - 32. */
317
    .long   trap        /* Trap Instruction Vectors 1                   - 33. */
318
    .long   trap        /* Trap Instruction Vectors 2                   - 34. */
319
    .long   trap        /* Trap Instruction Vectors 3                   - 35. */
320
    .long   trap        /* Trap Instruction Vectors 4                   - 36. */
321
    .long   trap        /* Trap Instruction Vectors 5                   - 37. */
322
    .long   trap        /* Trap Instruction Vectors 6                   - 38. */
323
    .long   trap        /* Trap Instruction Vectors 7                   - 39. */
324
    .long   trap        /* Trap Instruction Vectors 8                   - 40. */
325
    .long   trap        /* Trap Instruction Vectors 9                   - 41. */
326
    .long   trap        /* Trap Instruction Vectors 10                  - 42. */
327
    .long   trap        /* Trap Instruction Vectors 11                  - 43. */
328
    .long   trap        /* Trap Instruction Vectors 12                  - 44. */
329
    .long   trap        /* Trap Instruction Vectors 13                  - 45. */
330
    .long   trap        /* Trap Instruction Vectors 14                  - 46. */
331
    .long   trap        /* Trap Instruction Vectors 15                  - 47. */
332
    .long   0           /* (Reserved for Coprocessor)                   - 48. */
333
    .long   0           /* (Reserved for Coprocessor)                   - 49. */
334
    .long   0           /* (Reserved for Coprocessor)                   - 50. */
335
    .long   0           /* (Reserved for Coprocessor)                   - 51. */
336
    .long   0           /* (Reserved for Coprocessor)                   - 52. */
337
    .long   0           /* (Reserved for Coprocessor)                   - 53. */
338
    .long   0           /* (Reserved for Coprocessor)                   - 54. */
339
    .long   0           /* (Reserved for Coprocessor)                   - 55. */
340
    .long   0           /* (Reserved for Coprocessor)                   - 56. */
341
    .long   0           /* (Reserved for Coprocessor)                   - 57. */
342
    .long   0           /* (Reserved for Coprocessor)                   - 58. */
343
    .long   0           /* (Unassigned, Reserved)                       - 59. */
344
    .long   0           /* (Unassigned, Reserved)                       - 60. */
345
    .long   0           /* (Unassigned, Reserved)                       - 61. */
346
    .long   0           /* (Unassigned, Reserved)                       - 62. */
347
    .long   0           /* (Unassigned, Reserved)                       - 63. */
348
    /*                  The assignment of these vectors to the CPM is         */
349
    /*                  dependent on the configuration of the CPM vba         */
350
    /*                          fields.                                       */
351
    .long   0           /* (User-Defined Vectors 1) CPM Error           - 64. */
352
    .long   0           /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
353
    .long   0           /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
354
    .long   0           /* (User-Defined Vectors 4) CPM SMC2 / PIP      - 67. */
355
    .long   0           /* (User-Defined Vectors 5) CPM SMC1            - 68. */
356
    .long   0           /* (User-Defined Vectors 6) CPM SPI             - 69. */
357
    .long   0           /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
358
    .long   0           /* (User-Defined Vectors 8) CPM Timer 4         - 71. */
359
    .long   0           /* (User-Defined Vectors 9) CPM Reserved        - 72. */
360
    .long   0           /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
361
    .long   0           /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
362
    .long   0           /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
363
    .long   0           /* (User-Defined Vectors 13) CPM Timer 3        - 76. */
364
    .long   0           /* (User-Defined Vectors 14) CPM Reserved       - 77. */
365
    .long   0           /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
366
    .long   0           /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
367
    .long   0           /* (User-Defined Vectors 17) CPM Reserved       - 80. */
368
    .long   0           /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
369
    .long   0           /* (User-Defined Vectors 19) CPM Timer 2        - 82. */
370
    .long   0           /* (User-Defined Vectors 21) CPM Reserved       - 83. */
371
    .long   0           /* (User-Defined Vectors 22) CPM IDMA2          - 84. */
372
    .long   0           /* (User-Defined Vectors 23) CPM IDMA1          - 85. */
373
    .long   0           /* (User-Defined Vectors 24) CPM SDMA Bus Err   - 86. */
374
    .long   0           /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
375
    .long   0           /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
376
    .long   0           /* (User-Defined Vectors 27) CPM Timer 1        - 89. */
377
    .long   0           /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
378
    .long   0           /* (User-Defined Vectors 29) CPM SCC 4          - 91. */
379
    .long   0           /* (User-Defined Vectors 30) CPM SCC 3          - 92. */
380
    .long   0           /* (User-Defined Vectors 31) CPM SCC 2          - 93. */
381
    .long   0           /* (User-Defined Vectors 32) CPM SCC 1          - 94. */
382
    .long   0           /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
383
    /*                  I don't think anything uses the vectors after here.   */
384
    .long   0           /* (User-Defined Vectors 34)                    - 96. */
385
    .long   0,0,0,0,0               /* (User-Defined Vectors 35  -  39). */
386
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 40  -  49). */
387
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 50  -  59). */
388
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 60  -  69). */
389
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 70  -  79). */
390
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 80  -  89). */
391
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 90  -  99). */
392
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 100 - 109). */
393
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 110 - 119). */
394
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 120 - 129). */
395
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 130 - 139). */
396
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 140 - 149). */
397
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 150 - 159). */
398
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 160 - 169). */
399
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 170 - 179). */
400
    .long   0,0,0,0,0,0,0,0,0,0     /* (User-Defined Vectors 180 - 189). */
401
    .long   0,0,0                   /* (User-Defined Vectors 190 - 192). */
402
.text
403
ignore: rte
404

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