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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/microblaze/lib/umodsi3.S
10817 views
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#include <linux/linkage.h>

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/*

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 * Unsigned modulo operation for 32 bit integers.

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 *	Input :	op1 in Reg r5

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 *		op2 in Reg r6

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 *	Output: op1 mod op2 in Reg r3

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 */

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	.text

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	.globl	__umodsi3

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	.type __umodsi3, @function

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	.ent __umodsi3

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__umodsi3:

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	.frame	r1, 0, r15

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	addik	r1, r1, -12

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	swi	r29, r1, 0

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	swi	r30, r1, 4

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	swi	r31, r1, 8

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	beqi	r6, div_by_zero /* div_by_zero - division error */

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	beqid	r5, result_is_zero /* result is zero */

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	addik	r3, r0, 0 /* clear div */

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	addik	r30, r0, 0 /* clear mod */

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	addik	r29, r0, 32 /* initialize the loop count */

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/* check if r6 and r5 are equal /* if yes, return 0 */

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	rsub	r18, r5, r6

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	beqi	r18, return_here

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/* check if (uns)r6 is greater than (uns)r5. in that case, just return r5 */

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	xor	r18, r5, r6

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	bgeid	r18, 16

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	addik	r3, r5, 0

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	blti	r6, return_here

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	bri	$lcheckr6

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	rsub	r18, r5, r6 /* microblazecmp */

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	bgti	r18, return_here

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/* if r6 [bit 31] is set, then return result as r5-r6 */

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$lcheckr6:

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	bgtid	r6, div0

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	addik	r3, r0, 0

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	addik	r18, r0, 0x7fffffff

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	and	r5, r5, r18

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	and	r6, r6, r18

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	brid	return_here

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	rsub	r3, r6, r5

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/* first part: try to find the first '1' in the r5 */

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div0:

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	blti	r5, div2

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div1:

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	add	r5, r5, r5 /* left shift logical r5 */

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	bgeid	r5, div1

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	addik	r29, r29, -1

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div2:

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	/* left shift logical r5 get the '1' into the carry */

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	add	r5, r5, r5

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	addc	r3, r3, r3 /* move that bit into the mod register */

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	rsub	r31, r6, r3 /* try to subtract (r3 a r6) */

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	blti	r31, mod_too_small

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	/* move the r31 to mod since the result was positive */

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	or	r3, r0, r31

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	addik	r30, r30, 1

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mod_too_small:

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	addik	r29, r29, -1

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	beqi	r29, loop_end

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	add	r30, r30, r30 /* shift in the '1' into div */

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	bri	div2 /* div2 */

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loop_end:

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	bri	return_here

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div_by_zero:

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result_is_zero:

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	or	r3, r0, r0 /* set result to 0 */

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return_here:

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/* restore values of csrs and that of r3 and the divisor and the dividend */

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	lwi	r29, r1, 0

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	lwi	r30, r1, 4

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	lwi	r31, r1, 8

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	rtsd	r15, 8

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	addik	r1, r1, 12

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.size __umodsi3, . - __umodsi3

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.end __umodsi3

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